MH8S72DBFD-7 Datasheet, PDF (1/56 Pages) Mitsubishi Electric Semiconductor – 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH8S72DBFD is 8388608 - word x 72-bit Sy nchronous
DRAM module. This consist of nine industry standard
8M x 8 Sy nchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package prov ides any
application where high densities and large of quantities memory
are required.
This is a socket-ty pe memory m odule ,suitable f or easy
interchange or addition of m odule.
FEATURES
Type name
MH8S72DBFD-7
MH8S72DBFD-8
Max.
Frequency
100MHz
100MHz
CLK
Access Time
[component level]
6ns (CL = 2, 3)
6ns (CL = 3)
Utilizes industry standard 8M X 8 Synchronous DRAMs in
TSOP package , industry standard Resistered buffer in TSSOP
package and industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst W rite / Single W rite(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC/100 specification.
(module Spec. Rev. 1.2 and SPD 1.2A)
APPLICATION
Main memory or graphic memory in computer systems
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999 ₁