MH8S72DCFD-6 Datasheet, PDF (38/56 Pages) Mitsubishi Electric Semiconductor – 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
tRRD
tRCD
/WE
CKE
DQM
DQM read latency=3
A0-9
X
XY
YY
Y
Y
Y
A10
X
X
A11
X
X
BA0,1
0
DQ
REGE
10
00
1
0
0
Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q0
D0
ACT#0
READ#0 READ#0 READ#0
READ#0
WRITE#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
MIT-DS-0350-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
30/Sep. /1999 ₃₈