MH8S72DCFD-6 Datasheet, PDF (1/56 Pages) Mitsubishi Electric Semiconductor – 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH8S72DCFD is 8388608 - word x 72-bit Sy nchronous
DRAM module. This consist of nine industry standard
8M x 8 Sy nchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package prov ides any
application where high densities and large of quantities memory
are required.
This is a socket-ty pe memory m odule ,suitable f or easy
interchange or addition of m odule.
FEATURES
Type name
Max.
Frequency
Access Time from CLK
[component level]
MH8S72DCFD-6
133MHz
5.4ns
(CL = 4 at Latch mode)
Utilizes industry standard 8M X 8 Synchronous DRAMs in TSOP
package , industry standard Resistered buffer in TSSOP
package,industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
Max.Clock frequency 133MHz
Fully synchronous operation referenced to clock rising edge
4-bank operation controlled by BA0,BA1(Bank Address)
/CAS latency -2/3(programmable,at buffer mode)
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst type- Sequential and interleave burst (programmable)
Random column access
Burst W rite / Single W rite(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC133 specification.
APPLICATION
Main memory or graphic memory in computer systems
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
MIT-DS-0350-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999 ₁