M65863FP Datasheet, PDF (36/61 Pages) Mitsubishi Electric Semiconductor – Dolby Digital Decoder

Product Note
April 1998
M65863FP
Dolby Digital Decoder
1/fs
LRCK
2LRCK
2BCLK
MSB
LSB
DOLR
Lch
Rch
Cch
SW
DOSS
MSB
LSB
SLch
16 24
cycles
SRch
32cycles
Figure 5.10 I²S Format Interface Between M65863FP and DAC(dacform[0]=1)
5.2.3 Digital Audio Interface
M65863FP outputs either of 2 input data streams from DOTX. The selection of the input data streams
desponds on the content of inportsel(Control register).
1) When inportsel(control register) is 00 or 01 (DIR I/F input), M65863FP bypasses the input stream from
DIRX to DOTX.
2) When inportsel(control register) is 10 (DEMUX I/F input), M65863FP formats the input data stream in
IEC958(S/PDIF) and outputs it.
Table 5.1 and figure 5.11 show the format of consumer mode and the format for consumer digital audio
products, respectively.
Table 5.1 Format of IEC958 (S/P DIF) Consumer Mode
Symbol
Bits
Description
Sync preamble 4 There are 3 types (B,M,W) depending on the character of the subframe (see table 5.2)
Aux data
Linear PCM word
Validity flag
4 Auxiliary information or extension of audio data. This value will be "0000"
Dolby Digital (AC-3) data. MSB in slot 27. If the length of data is less than 20, zero is
asserted to the LSB side. AC-3 data is placed into slots 12-27 (16bits) of the sub-frames
20
1 0 : Dolby Digital (AC-3) Data are reliable, 1 : Dolby Digital (AC-3) data are unreliable
User data
One bit of channel
status word
1 This value is 0 in all subframes
Supports consumer mode (value is 0). C bit of subframe within the same channel indicates
1
as follows (see figure 5.11). The bit fields except for CR, category code and sampling rate
are all 0.
Parity bit
CR(Copyright)
0 : Protected, 1 :Not protected
Category code
This value is same as internal register
Default values are all zero
Sampling rate
0000 : 44.1kHz, 0100 : 48kHz, 1100 : 32kHz
This parity bit is due to be an even number of "1" and "0" between slot 4 and slot 31 in
1 subframe
MITSUBISHI ELECTRIC CORPORATION
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