M65863FP Datasheet, PDF (19/61 Pages) Mitsubishi Electric Semiconductor – Dolby Digital Decoder

Product Note
April 1998
M65863FP
Dolby Digital Decoder
Number of PCM Output Bits (outbitlen)
2 bits
Specify the output bit length. Default value is 00 (16 bits output). This field can be changed at any time.
outbitlen
Description
00
16 bit
01
18 bit
10
20 bit
11
24 bit
address h'15
DSP/DAC Clock Mode (dacclkmode)
1 bit
Specify the LR clock and bit clock to be used in the DAC/DSP interface. When dacclkmode=0,
M65863FP becomes the clock master and divides the audio master clock to generate LR clock (LRCK)/bit
clock (BCLK). When dacclkmode=1, M65863FP becomes the slave and uses the DIR/ADC input clocks
(ALRCK, ACLK) as the LR clock and bit clock, respectively. In the default setting, M65863FP becomes
the clock master. Set this value only once when M65863FP is in the initial status.
dacclkmode
0
1
Description
Clock master
Slave
Selection of DSP/DAC Interface (dspif)
1 bit
Specify the output interface mode. Default value is 0 (DAC interface). This field can be changed at any
time.
dspif
0
1
Description
DAC/IF
DSP I/F
DIR/ADC Data Input Format (dirform)
3 bits
Specify the format of data input from DIR/ADC. Default value is 000 (MSB first right-justified, when
ALRCK is 1, Lch input). This field can be changed at any time.
dirform
000
001
010
011
100
101
110
111
Description
MSB first right-justified format (when ALRCK is 1, Lch input)
LSB first right-justified format (when ALRCK is 1, Lch input)
I2S format (when ALRCK is 1, Lch input)
Reserved
MSB first right-justified format (when ALRCK is 0, Lch input)
MSB first right-justified format (when ALRCK is 0, Lch input)
I2S first right-justified format (when ALRCK is 0, Lch input)
Reserved
MITSUBISHI ELECTRIC CORPORATION
18