M66290AGP Datasheet, PDF (34/53 Pages) Mitsubishi Electric Semiconductor – USB DEVICE CONTROLLER

MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Bit
Bit
Name
Name
Function
12 BCLR
Buffer clear
If the selected endpoint is set to IN, when "1" is written into
this bit, the IN buffer effective state flag and the data (byte)
which is written are cleared.
If IVAL="1" and BCLR="1" is written at the same time, data
is cleared but the IN buffer effective state flag is set.
(This is effective to transmit 0 length data)
If the selected endpoint is set to OUT, when "1" is written into
this bit, the OUT buffer effective state flag and the read data (byte)
are cleared.
If it is set to double buffer, the state of write/read enable buffer
for CPU is cleared.
To set the EPi_ACLR, USB bus buffer is cleared.
This bit is not changed when "0" is written.
Reset
W/R
H/W S/W USB
W/R 0 - -
If this bit is "0", access to CPU_FIFO data register is available.
And if this bit is "0", the bit of IVAL and CPU_DTLN bit shows the
effective value.
11 Creq CPU_FIFO ready
When read or write to CPU_FIFO register, 200ns (min) of cycle
time is needed. (Continuous access at 5MHz is available)
If the access end point is changed, 200ns (min) of recovery
time is needed.
R1--
CPU_DTL
10 to 0
N[10:0]
CPU_FIFO
receive data
leng th
When read this register, receive data length (byte) appears.
When RCNT mode is set, every time when read CPU_FIFO
register, it is counted down by -1 (8-bit mode) or by -2 (16-bit mode).
If RCNT mode is not set, this register turns to 000h after all of
received data is read.
This bit shows effective value when Creq bit is "0".
R 000h - -
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