MH64S64APFH-6 Datasheet, PDF (30/52 Pages) Mitsubishi Electric Semiconductor – 4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S64APFH-6,-6L,-7,-7L
4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQMB0-7 masks input data word by word.
DQMB0-7 to Data In latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
Write
READ
DQMB0-7
DQ
D0
D2 D3
Q0 Q1
Q3
masked by DQMB=H
disabled by DQMB=H
MIT-DS-0392-0.1
MITSUBISHI
ELECTRIC
( 30 / 52 )
16.Apr.2000