M32000D4BFP-80 Datasheet, PDF (28/44 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Programmable I/O port
The M32000D4BFP-80 has two programmable I/O ports (PP0, PP1).
Each port can be set as input or output.
programmable I/O port direction control register 0 (PPCR0)
< address: H'FFFF FFE3>
D24 D25 D26 D27 D28 D29 D30 D31
PP0C
programmable I/O port direction control register 1 (PPCR1)
< address: H'FFFF FFE7>
D24 D25 D26 D27 D28 D29 D30 D31
PP1C
D
24 - 30
31
bit name
Not assigned.
PP0C, PP1C
(port I/O direction)
<at reset: H'00>
function
RW
0!
0: input port
1: output port
R = 0 ... "0" when reading R = ... read enabled
W = ... write enabled W = ! : write disabled
Fig. 30 Programmable I/O port direction control register
programmable I/O port data register 0 (PPDR0)
< address: H'FFFF FFEB>
D24 D25 D26 D27 D28 D29 D30 D31
PP0D
Reset
____
When an "L" level is input to RST, the M32000D4BFP-80 switches to
the reset state. The reset state is released when an "H" level is input
____
to RST, and the program is executed from the EIT vector entry of the
reset interrupt. All internal resources including the internal PLL (4x
clock generator) are initialized. In order to stabilize PLL oscillation,
____
the "L" input to RST should last a minimum of 2 ms after the clock
input to CLKIN stabilizes and VCC stabilizes to the specified voltage
level.
Table 2 Internal state after reset
internal resources
DRAM
cache memory
general purpose
registers
(R0 - R15)
control registers PSW (CR0)
CBR (CR1)
SPI (CR2)
SPU (CR3)
BPC (CR6)
state
undefined
invalid
(purged all)
undefined
B'0000 0000 0000 0000 ??00 000? 0000 0000
(BSM, BIE, and BC are undefined)
H'0000 0000
undefined
undefined
undefined
I/O registers
PC
master mode:
execute from address H'7FFF FFF0
slave mode:
wait for interrupt input at address
H'7FFF FFF0
• execute from_{__}a_{_}ddress H'0000 0010
by inputting SBI signal
• execute from_{__}a_{_}ddress H'0000 0080
by inputting INT signal
ACC
(accumulator) undefined
PPCR0, PPCR1 H'00 (input)
PPDR0, PPDR1 B'0000 000? (depends on input
MLCR
pin state)
_____
H'00 (HREQ exclusive lock mode)
MPMR
H'00 (normal operation)
MCCR
H'01 (cache-off mode)
programmable I/O port data register 1 (PPDR1)
< address: H'FFFF FFEF>
D24 D25 D26 D27 D28 D29 D30 D31
PP1D
D
24 - 30
31
bit name
Not assigned.
PP0D, PP1D
(port data)
<at reset: B'0000 000?>
function
RW
0!
0: data = "0"
1: data = "1"
R = 0 ... "0" when reading R = ... read enabled
W = ... write enabled W = ! : write disabled
Fig. 31 Programmable I/O port data register
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