M5M4V4405CJ Datasheet, PDF (25/27 Pages) Mitsubishi Electric Semiconductor – EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM

MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Test Mode Set Cycle (Note 34)
RAS
CAS
A0~A9
W
tRP
VIH
VIL
tRPC _tCSR
VIH
VIL
tCPN
tCHR
VIH
VIL
tRCH
VIH
VIL
tWSR tWHR
tRC
tRAS
tRP
tRPC
tCRP
tASR
ROW
COLUMN
ADDRESS ADDRESS
tRCS
DQ1~DQ4 ^VIH
(INPUTS)
VIL
DQ1~DQ4 ^VOH
(OUTPUTS) _VOL
VIH
OE
VIL
tOFF
tOEZ
Hi-Z
Note 34: The cycle is also avaiilable for initialization cycle, but in this case device enters test mode.
The test mode function is initiated with a W and CAS before RAS cycle(WCBR cycle) as specified above timing diagram.
The test mode function is terminated by either a CAS before RAS(CBR) refresh or a RAS only refresh cycle.
During the test mode, the device is internally organized as 4-bits wide (256 kilobytes deep) for each DQ (input / output) port.
No addressing of A0, A1(column only) is required.
During a write cycle, data on the each DQ (input) pin is written in parallel into all 4-bits for each DQ port and can be written
independently for each DQ port.
During a read cycle, the each DQ (output) pin indicates independently a HIGH state if all 4-bits are equal, and a LOW state
if any bits differ.
During the test mode operation, a WCBR cycle is used to perform refresh.