M2V56S20ATP Datasheet, PDF (25/49 Pages) Mitsubishi Electric Semiconductor – 256M Synchronous DRAM

SDRAM (Rev.1.01)
Single Data Rate
Jul '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H)
command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbit
memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-
refresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any
command must not be issued before tRFC from the REFA command.
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-12
BA0-1
Auto-Refresh
NOP or DESELECT
minimum tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
MITSUBISHI ELECTRIC
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