M2V56S20ATP Datasheet, PDF (1/49 Pages) Mitsubishi Electric Semiconductor – 256M Synchronous DRAM

SDRAM (Rev.1.01)
Single Data Rate
Jul '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20ATP is a 4-bank x 16777216-word x 4-bit,
M2V56S30ATP is a 4-bank x 8388608-word x 8-bit,
M2V56S40ATP is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M2V56S20/30/40ATP achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),
166MHz(-5) and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v±0.3V power supply
- Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
M2V56S20/30/40ATP-5
Max. Frequency
@CL2
133 MHz
Max. Frequency
@CL3
166 MHz
Standard
PC133 (CL2)
M2V56S20/30/40ATP-6
100MHz
133 MHz
PC133 (CL3)
M2V56S20/30/40ATP-7
100 MHz
100MHz
PC100 (CL2)
MITSUBISHI ELECTRIC
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