M2V56S20TP Datasheet, PDF (18/49 Pages) Mitsubishi Electric Semiconductor – 256M Synchronous DRAM

SDRAM (Rev.1.1)
Single Data Rate
Feb.2000
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any active bank. Random column access is
allowed. READ to READ interval is minimum 1 CLK.
Read interrupted by Read (CL=2, BL=4)
CLK
Command
READ
READ READ
A0-9,11-12
Ya
Yb Yc
A10
0
0
0
BA0-1
00
00 10
DQ
Qa0 Qa1 Qa2 Qb0 Qc0 Qc1 Qc2 Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access is allowed.
In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention.
The output is disabled automatically 2 cycle after WRITE assertion.
Read interrupted by Write (CL=2, BL=4)
CLK
Command ACT
READ
Write
A0-9,11-12 Xa
Ya
Ya
A10 Xa
0
0
BA0-1 00
00
00
DQM
DQ
Qa0
Da0 Da1 Da2 Da3
Output disable by DQM by WRITE
MITSUBISHI ELECTRIC
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