MH2S64CZTJ-12 Datasheet, PDF (17/45 Pages) Mitsubishi Electric Semiconductor – 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH2S64CZTJ/CWZTJ-12,-15,-1539
134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM
Dual Bank Interleaving READ (BL=4, CL=3)
CK
Command
A0-9
A10
ACT
Xa
tRCD
READ ACT
Y Xb
Xa
0
Xb
READ PRE
Y
0
0
BA
0
01
1
0
DQ
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
/CAS latency
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CK
Command
A0-9
A10
BA
DQ
ACT
Xa
tRCD
READ
Y
Xa
1
0
0
ACT
tRP
Xa
Xa
0
Qa0 Qa1 Qa2 Qa3
CK
Command
CL=4 DQ
CL=3 DQ
CL=2 DQ
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
ACT
READ
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
MIT-DS-0019-0.4
Internal Precharge Start Timing
MITSUBISHI
ELECTRIC
( 17 / 45 )
Oct.28.1996