MH2S64CZTJ-12 Datasheet, PDF (1/45 Pages) Mitsubishi Electric Semiconductor – 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH2S64CZTJ/CWZTJ-12,-15,-1539
134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH2S64CZTJ/CWZTJ is 2097152-word by
64-bit Synchronous DRAM module. This consists of
eight industry standard 2Mx8 Synchronous DRAMs
in TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-12
83MHz
8ns(CL=3)
-15
67MHz
9.5ns (CL=2)
85pin 1pin
94pin
95pin
10pin
11pin
-1539
67MHz
9ns (CL=3)
Utilizes industry standard 2M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
124pin 40pin
125pin 41pin
Clock frequency 83MHz/67MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 1/2/3(programmable)
Burst length- 1/2/4/8(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
168pin 84pin
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
SPD table
Byte No.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 126 127
MH2S64CZTJ/CWZTJ-12 80 08 04 0C 09 01 40 00 01 C0 80 00 80 00 06 01 05 02 06 01 01 83 06
MH2S64CZTJ/CWZTJ-15 80 08 04 0C 09 01 40 00 01 F0 95 00 80 00 06 01 05 02 06 01 01 66 06
MH2S64CZTJ/CWZTJ-1539 80 08 04 0C 09 01 40 00 01 F0 90 00 80 00 04 01 05 02 04 01 01 66 04
MIT-DS-0019-0.4
MITSUBISHI
ELECTRIC
Oct.28.1996
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