M37920FCCGP Datasheet, PDF (156/158 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION

Corrections and Supplementary Explanation for M37920FxC Datasheet (REV.A) NO.4
Page
Page 92,
Left column,
Lines 28, 29
Error
Correction
••••••• selected.
Bit 2 of the DRAM control register is the access mode
select bit. When bit 2 is “0”, normal access is selected,
when it is “1”, fast page access is selected. When the fast
page access is selected, the access supporting the fast
page access mode of DRAM is performed, if the range
which can be specified with the same row address is
continuously accessed. If the row address changes
during the fast page access, the new row addresses will
be output again after that fast page access is terminated.
Then, the fast page access will restart.
Figure 93 shows an operating waveformexample of the
DRAM control signals and address bus in the fast page
access.
Bit 4 of the DRAM •••••••
••••••• selected.
Bit 4 of the DRAM •••••••
Page 95,
Fig. 90
2 10
0
DRAM control register
2 10
00
DRAM control register
Access mode select bit
0: Normal access
1: Fast page access
Fix this bit to “0”.
Page 99,
Right column,
Lines 1 to 3
When the waveform output select bits are set to “11” (bit 1
= bit 0 = “1”), RTP13 to RTP10, RTP03, and RTP02
become pulse output port pins.
When the waveform output •••••••••
When the waveform output select bits are set to “11” (bit 1
= bit 0 = “1”), pulse output port pins are divided into two
groups; one consists of RTP13 to RTP10, RTP03, RTP02
and the other consists of RTP01 and RTP00.
When the waveform output •••••••••
Operating waveform example of DRAM control signals
and address bus in fast page access
(Deleted)
Page 117,
Right column,
Lines 15 to 17
M37920F8CGP, M37920F8CHP : block configuration of
internal flash memory
area if the user uses the flash memory serial I/O mode.
Note that, when the boot ROM area is read •••••••••
Page 118 The reset input pin. Input “H” after “L” is input.
RESET;
[Function]
P42;
[Function]
This is an I/O pin for serial data.
P44; This is an input pin for a serial clock. Connect this pin to
[Function] ^{VCC via a resistor (about 1 kΩ).}
NMI;
[Function]
Page 122,
Boot mode
Input “H”.
(Lines 22, 23)
program the user ROM area.
Page 122,
Fig. 120,
Note 4
4: Valid only when bit 1 = “1”. Set bit 3 to “1” (reset), and
then clear to “0”.
(Deleted)
area if the user uses the flash memory serial I/O mode.
Addresses FFB016 to FFBF16 are the reserved area for
the serial programmer. Therefore, when the user uses
the flash memory serial I/O mode, do not program to this
area.
Note that, when the boot ROM area is read •••••••••
The reset input pin.
This is an I/O pin for serial data. Connect this pin to VCC
via a resistor (about 1 kΩ).
This is an input pin for a serial clock.
Input “H”, or leave this pin open.
(Lines 22, 23)
program the user ROM area.
After reset removal, be sure not to change the status at
pins MD0 and MD1.
4: Valid only when bit 1 = “1”. Set bit 3 to “1” (reset), and
then clear to “0”. This bit 3 must be controlled with the
CPU reprogramming mode select bit (bit 1) = “1”.
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