M37920FCCGP Datasheet, PDF (155/158 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION

Corrections and Supplementary Explanation for M37920FxC Datasheet (REV.A) NO.3
Page
Error
Correction
Page 28,
Fig. 12
Page 35,
Fig. 17,
Area CSx start
address register
(x = 0 to 3)
2 10
Area CSx start address register
(x = 0, 3)
These bits determine •••••
•
•
Notes 1: After reset, this bit’s contents can be switched
only once. During the software execution, be
sure not to switch this bit’s contents.
2: In the single-chip mode, these bits’ functions
are disabled regardless of these bits’ contents.
3: While VSS level voltage is applied to pin MD0,
each of these bits is “0” at reset. While VCC
level voltage is applied to pin MD0, on the
other hand, each of these bits is “1” at reset.
4: In the memory expansion or microprocessor
mode, if this bit’s contents is switched from “1”
to “0”, this bit will be cleared to “0”.
After this clearance, this bit cannot return to
“1”. If it is necessary to set this bit to “1”, be
sure to reset the microcomputer.
5: In the microprocessor mode, this bit is invalid.
When the internal flash memory is reprogram-
med in the CPU reprogramming mode, be
sure to clear this bit to “0”.
2 10
Area CS3 start address register
(x = 0, 3)
“0” at read.
These bits determine •••••
•
•
2 10
Area CSx start address register
(x = 1, 2)
When mode 0 is •••••
•
•
Page 51,
Left column,
Lines 14, 17,
22
Page 61,
Interrupt
request at
completion of
reception
••••• timer Ai start bit •••••
(Line 9)
••••• control register 0 (UART receive interrupt mode
select bit) •••••
(Lines 18, 20)
••••• UARTi receive interrupt mode select bit •••••
Page 67,
Fig. 63
Ladder network
2 10
Area CSx start address register
(x = 1, 2)
“0” at read.
When mode 0 is •••••
•
•
••••• count start bit •••••
(Line 9)
••••• control register 0 (UARTk receive interrupt mode
select bit) •••••
(Lines 18, 20)
••••• UARTk receive interrupt mode select bit •••••
Resistor ladder network
Page 68, (Lines 2, 3)
VREF connection _{••••••• the ladder network or not •••••••••••}
(Lines 2, 3)
••••••• the resistor ladder network or not •••••••••••
(Line 7)
the ladder network can be cut off by disconnecting ladder
network •••••••
(Line 7)
the resistor ladder network can be cut off by disconnect-
ing resistor ladder network •••••••
(3/6)