M5M5T5636UG-25 Datasheet, PDF (15/23 Pages) Mitsubishi Electric Semiconductor – 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
JTAG PORT OPERATION
Overview
The JTAG Port on this SRAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but dose not implement all of the function required for 1149.1 compliance. The JTAG Port
interfaces with conventional CMOS logic level signaling.
Disabling the JTAG port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. To
assure normal operation of the SRAM with the JTAG Port unused, the TCK, TDI and TMS pins may be left floating or tied to High. The
TDO pin should be left unconnected.
JTAG Pin Description
Test Clock (TCK)
The TCK input is clock for all TAP events. All inputs are captured on the rising edge of TCK and the Test Data Out (TDO) propagates from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP Controller state machine. An undriven TMS
input will produce the same result as a logic one input level.
Test Data In (TDI)
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between the TDI and TDO pins.
the register placed between the TDI and TDO pins is determined by the state of the TAP Controller state machine and the instruction that
is currently loaded in the TAP Instruction Resister (refer to the TAP Controller State Diagram). An undriven TDI Input will produce the
same result as a logic one input level.
Test Data Out (TDO)
The TDO output is active depending on the state of the TAP Controller state machine. Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed between the TDI and TDO pins.
Note:
This device dose not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.
JTAG Port Registers
Overview
The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequence of 1s and 0s
applied to TMS as TCK is strobed. Each of TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK
and push serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP Controller when it is moved into the Run-Test/Idle, or the
various data register states. Instructions are 3 bits long. The Instruction Resister can be loaded when it is placed between the TDI and
TDO pins. The Instruction Resister is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is
placed in Test-Logic-Reset state.
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MITSUBISHI
Advanced Information
ELECTRIC
M5M5T5636UG REV.0.1