M5M5T5636UG-25 Datasheet, PDF (1/23 Pages) Mitsubishi Electric Semiconductor – 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

2001.March Rev.0.1
Advanced Information
Notice: This is not final specification.
Some parametric limits are subject to change.
DESCRIPTION
The M5M5T5636UG is a family of 18M bit synchronous SRAMs
organized as 524288-words by 36-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads and
writes, or writes and reads. Mitsubishi's SRAMs are fabricated
with high performance, low power CMOS technology, providing
greater reliability. M5M5T5636UG operates on 2.5V power/ 1.8V
I/O supply or a single 2.5V power supply and are 2.5V CMOS
compatible.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 250, 225, and 200 MHz
• Fast access time: 2.6, 2.8, 3.2 ns
• Single 2.5V -5% and +5% power supply VDD
• Separate VDDQ for 2.5V or 1.8V I/O
• Individual byte write (BWa# - BWd#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need to
control G#
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
• JTAG boundary scan support
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
FUNCTION
Synchronous circuitry allows for precise cycle control
triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs, all
Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#). Write operations are controlled by
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous self-
timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the
SRAM in the power-down state.The Linear Burst order (LBO#) is
DC operated pin. LBO# pin will allow the choice of either an
interleaved burst, or a linear burst.
All read, write and deselect cycles are initiated by the ADV
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
Package
165(11x15) bump BGA
Body Size (13mm x 15mm)
Bump Pitch 1.0mm
PART NAME TABLE
Part Name
Frequency
M5M5T5636UG - 25 250MHz
Access
2.6ns
Cycle
4.0ns
Active Current
(max.)
400mA
Standby Current
(max.)
20mA
M5M5T5636UG - 22 225MHz
2.8ns
4.4ns
380mA
20mA
M5M5T5636UG - 20 200MHz
3.2ns
5.0ns
360mA
20mA
1
MITSUBISHI
Advanced Information
ELECTRIC
M5M5T5636UG REV.0.1