M2V64S20BTP-6 Datasheet, PDF (11/52 Pages) Mitsubishi Electric Semiconductor – 64M bit Synchronous DRAM

PC133 SDRAM (Rev.0.5)
Oct. '99
64M bit Synchronous DRAM
MITSUBISHI LSIs
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
FUNCTION TRUTH TABLE for CKE
CKE CKE
Current State
n-1 n
SELF-
HX
REFRESH*1 _L
H
LH
LH
LH
LH
L
L
POWER
DOWN
HX
LH
L
L
ALL BANKS H H
IDLE*2
HL
HL
HL
HL
HL
HL
L
X
ANY STATE ^H
H
other than
H
L
listed above
L
H
L
L
/CS /RAS /CAS /WE
X
X
X
X
H
X
X
X
LHHH
L HH L
L
H
L
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
H
H
X
X
X
LHHH
L HH L
L
H
L
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Add
Action
X INVALID
X Exit Self-Refresh (Idle after tRC)
X Exit Self-Refresh (Idle after tRC)
X ILLEGAL
X ILLEGAL
X ILLEGAL
X NOP (Maintain Self-Refresh)
X INVALID
X Exit Power Down to Idle
X NOP (Maintain Self-Refresh)
X Refer to Function Truth Table
X Enter Self-Refresh
X Enter Power Down
X Enter Power Down
X ILLEGAL
X ILLEGAL
X ILLEGAL
X Refer to Current State =Power Down
X Refer to Function Truth Table
X Begin CLK Suspend at Next Cycle*3
X Exit CLK Suspend at Next Cycle*3
X Maintain CLK Suspend
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MITSUBISHI ELECTRIC
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