M5M44405CJ Datasheet, PDF (10/27 Pages) Mitsubishi Electric Semiconductor – EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM

MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Timing Diagram (Note 32)
Read Cycle
RAS
VIH–
VIL–
CAS
VIH–
VIL–
A0~A9
VIH–
VIL–
tCRP
tRCD
tASR
tRAH
ROW
ADDRESS
tRAD
tRC
tRAS
tCSH
tRSH
tCAS
tASC
tCAH
COLUMN
ADDRESS
tRAL
tCAL
tRCS
VIH–
W
VIL–
tRP
tCRP
tASR
ROW
ADDRESS
tRRH
tRCH
DQ1~DQ4
(INPUTS)
VIH–
VIL–
DQ1~DQ4 VOH–
(OUTPUTS) _VOL–
VIH–
OE
VIL–
tDZC
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
tOEA
Hi-Z
tREZ
tOHR
DATA VALID
tOCH
tCDD
tWEZ
tOFF
tOHC
Hi-Z
tOHO
tOEZ
tODD
tORH
Note 32
Indicates the don't care input.
VIH(min) ≤ VIN ≤ VIH(max) or VIL(min) ≤ VIN ≤ VIL(max)
Indicates the invalid output.
10
M5M44405CJ,TP-5,-5S:Under development