M2S28D20ATP Datasheet, PDF (10/36 Pages) Mitsubishi Electric Semiconductor – 128M Double Data Rate Synchronous DRAM

DDR SDRAM (Rev.0.1)
Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command
REFRESHING H X X X X
DESEL
L H H HX
NOP
L H H L BA
TERM
L H L X BA, CA, A10 READ / WRITE
L L H H BA, RA
ACT
L L H L BA, A10
PRE / PREA
L L L HX
REFA
LL
L L ^{Op-Code, Mode-} MRS
Add
MODE
H X X XX
DESEL
REGISTER L H H H X
NOP
SETTING _{L H H L BA}
TERM
L H L X BA, CA, A10 READ / WRITE
L L H H BA, RA
ACT
L L H L BA, A10
PRE / PREA
L L L HX
REFA
LL
Op-Code, Mode-
L L _Add
MRS
Action
NOP (Idle after tRC)
NOP (Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Row Active after tRSC)
NOP (Row Active after tRSC)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Notes
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC
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