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MH32S72DBFA-7 Datasheet, PDF (1/56 Pages) Mitsubishi Electric Semiconductor – 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32S72DBFA -7,-8
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH32S72DBFA is 33554432 - word x 72-bit
Sy nchronous DRAM stacked structural module. This
consist of t hirty -six industry standard 16M x 4
Sy nchronous DRAMs in TSOP.
The stacked structure of TSOP on a card edge dual in-
line package prov ides any application where high
densities and large of quantities memory are required.
This is a socket-ty pe memory m odule ,suitable f or
easy interchange or addition of m odule.
FEATURES
Type name
MH32S72DBFA-7
MH32S72DBFA-8
Max.
Frequency
100MHz
CLK
Access Time
[latch mode]
(CL = 4)
6ns
100MHz
6ns
Utilizes industry standard 16M X 4 Synchronous DRAMs in
TSOP package , industry standard Resister in TSSOP package ,
and industry standard PLL in TSSOP package.
Single 3.3V +/- 0.3V supply
Burst length 1/2/4/8/Full Page (programmable)
Burst type sequential / interleave (programmable)
Column access random
Burst W rite / Single W rite (programmable)
Auto precharge / Auto bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
4096 refresh cycles every 64ms
Intel specifiation(rev. 1.2)compliant PCB and SPD 1.2A
APPLICATION
Main memory unit for computers, Microcomputer memory.
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
MIT-DS-348-0.0
MITSUBISHI
ELECTRIC
29/Sep. /1999 1