MH32S64APFB-7 Datasheet, PDF (1/55 Pages) Mitsubishi Electric Semiconductor – 2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32S64APFB -7,-8
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH32S64APFB is 33554432 - word by 64-bit
Synchronous DRAM module. This consists of
sixteen industry standard 16Mx8 Synchronous
DRAMs in Small TSOP and one industory
standard EEPROM in TSSOP.
The mounting of Small TSOP on a card edge
Dual Inline package provides any application
where high densities and large quantities of
memory are required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
FEATURES
-7,-7L
-8,-8L
Frequency
100MHz
100MHz
CLK Access Time
(Component SDRAM)
6.0ns(CL=3)
6.0ns(CL=3)
PC100 Compliant
Utilizes industry standard 16M x 8 Sy nchronous DRAMs
Small TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
1
(Back)
2
MIT-DS-0358-0.2
MITSUBISHI
ELECTRIC
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16.Mar.2000