MH1S72CPG-10 Datasheet, PDF (1/47 Pages) Mitsubishi Electric Semiconductor – 75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
DESCRIPTION
The MH1S72CPG is 1048576-word by 64-bit
Synchronous DRAM module. This consists of five
industry standard 1Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-10
100MHz
8ns(CL=3)
85pin 1pin
94pin
95pin
10pin
11pin
-12
83MHz
8ns (CL=3)
-15
67MHz
9ns (CL=3)
Utilizes industry standard 1M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
124pin 40pin
125pin 41pin
Clock frequency 100MHz/83MHz/67MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 1/2/3(programmable)
Burst length- 1/2/4/8(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
168pin 84pin
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
Module item "-10","-12" , and "-15" show mounted SDRAM devices Cycle time(min.).
MIT-DS-0089-3.0
MITSUBISHI
ELECTRIC
( 1 / 47 )
28.Mar.1997