M66007P Datasheet, PDF (1/6 Pages) Mitsubishi Electric Semiconductor – 12-BIT INPUT EXPANDER

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M660M0676P00/7FPP/FP
12-1B2IT-BIINTPINUPTUETXEPAXNPADNEDRER
DESCRIPTION
The M66007 is a semiconductor integrated circuit providing
the 12-bit parallel input-serial output shift register function.
This product is completely designed with CMOS to sharply
reduce power consumption compared with bipolar or Bi-
CMOS product.
The M66007, developed as an input only expander IC neces-
sary for microcomputer periphery, is widely applicable as a
data parallel/serial conversion IC.
FEATURES
• Control signals of only two pins including LE/D and CLK
• Low power consumption of 50 µW/package maximum
(Vcc=5V, Ta=25°C at time of standstill)
• Schmitt triggered input (LE/D, CLK, D0 to D11)
• Wide operating supply voltage range (Vcc=2~6V)
• Wide operating temperature range (Ta=–20~75°C)
APPLICATION
Parallel/serial data conversion for microcomputer periphery
FUNCTION
The M66007 uses a silicon gate CMOS process to achieve
low power consumption and high noise margin.
For control signals, this IC adopts only the two pins of latch
input/serial data output LE/D and clock input CLK. Each bit
of shift register of 12-bit parallel input-serial output consists of
flip-flop for shift.
When LE/D is placed in input mode, CLK is set to “H” and LE/
D changes from “H” to “L”, the status of parallel data inputs D0
to D11 at that time is latched with the flip-flop for shift and LE/
D is switched to output mode to output “L”.
PIN CONFIGURATION (TOP VIEW)
LATCH INPUT/
SERIAL DATA OUTPUT
LE/D
↔
1
CLOCK INPUT CLK → 2
PARALLEL
DATA INPUT

D0
D1
D2
D3
D4
→
→
→
→
→
3
4
5
6
7
GND 8
LE/D
CLK D11
D0 D10
D1 D9
D2 D8
D3 D7
D4 D6
D5
16 VCC
15
14
13
12
11
10
9
←
←
←
←
←
←
←
DDDDDDD119876510^{}
PARALLEL
DATA INPUT
Outline 16P4
16P2N-A
After this, change of CLK from “H” to “L” makes the shift regis-
ter perform shift operation and LE/D outputs the contents of
the shift register from D0 in order.
In addition, the shift operation for up to the 12th bit is carried
out and then LE/D is switched to the input mode at the falling
edge of CLK of the 13th bit.
When power is turned on, the input/output mode of LE/D is
indeterminate. However, detection of 13 or more falling
edges of CLK sets LE/D in the input mode.
BLOCK DIAGRAM
Vcc
LATCH INPUT/
LE/D 1
SERIAL DATA OUTPUT
CLOCK INPUT CLK 2
Vcc 16
GND 8
QP
CONTROL CIRCUIT
LE
LCLK
QN
SD
SQ
CLK
SHIFT REGISTER
D11 D10 D9 D8
D0
Q11 Q10 Q9 Q8
Q0
PARALLEL LATCH
LE
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
15 14 13 12 11 10 9 7 6 5 4 3
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PARALLEL DATA INPUT
1