M5M5V32R16J-10 Datasheet, PDF (1/8 Pages) Mitsubishi Electric Semiconductor – 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM

1997.01.22
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V32R16 is a family of 32768-word by 16-bit
static RAMs, fabricated with the high performance CMOS
process and designed for high speed application. These
devices operate on a single 3.3V supply, and are directly
TTL compatible.
They include a power down feature as well. In write
and read cycles, the lower and upper bytes are able
to be controled either togethe or separately by /LB
and /UB.
FEATURES
Fast access time M5M5V32R16J,TP-10 10ns(max)
M5M5V32R16J,TP-12 12ns(max)
M5M5V32R16J,TP-15 15ns(max)
Low power dissipation Active
297mW(typ)
Stand by
0.33mW(typ)
Single +3.3V power supply
Fully static operation : No clocks, No refresh
Common data I/O
Easy memory expansion by /S
Three-state outputs : OR-tie capability
OE prevents data contention in the I/O bus
Directly TTL compatible : All inputs and outputs
Separate control of lower and upper bytes by /LB and /UB
PIN CONFIGURATION (TOP VIEW)
N.C 1
A3 2
A2 3
ADDRESS
INPUTS
A1
4
CHIP
A0 5
SELECT
INPUTS
/S 6
DQ1
7
DATA
INPUTS/
DQ2
8
OUTPUTS DQ3
9
DQ4 10
(3.3V) Vcc 11
(0V) GND 12
DQ5 13
DATA
INPUTS/
DQ6 14
OUTPUTS DQ7 15
WRITE
DQ8 16
CONTROL
/W 17
INPUT
A14 18
ADDRESS A13 19
INPUTS _{A12 20}
A11 21
NC 22
44 A4
43
A5
ADDRESS
INPUTS
42 A6
41
/OE
OUTPUT
ENABLE
40
/UB ^BYTE
CONTROL
39 /LB INPUTS
38 DQ16
35
DQ15
DATA
INPUTS/
36
DQ14 OUTPUTS
35 DQ13
34 GND (0V)
33 Vcc (3.3V)
32 DQ12
31
DQ11
DATA
INPUTS/
30
DQ10 OUTPUTS
29 DQ9
28 NC
27 A7
26
A8
ADDRESS
25 A9
INPUTS
24 A10
23 NC
Outline 44P0K(J)
44P3W-H(TP)
APPLICATION
High-speed memory system
FUNCTION
The operation mode of the M5M5V32R16 is
determined by a combination of the device control
inputs /S, /W, /OE, /LB, and /UB. Each mode is
summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with low level /LB and/or low level /UB and low
level /S. The address must be set-up before write cycle
and must be stable during the entire cycle.
The data is latched into a cell on the traling edge of
/W, /LB, /UB or /S, whichever occurs first, requiring the
set-up and hold time relative to these edge to be
maintained. The output enable input /OE directly
controls the output stage. Setting the /OE at a high
level, the output stage is in a high impedance state, and
the data bus contention problem in the write cycle is
eliminated.
A read cycle is excuted by setting W at a high level
and /OE at a low level while /LB and/or /UB and /S are
in an active state. (/LB and/or /UB=L, /S=L)
PACKAGE
M5M5V32R16J : 44pin 400mil SOJ
M5M5V32R16VP: 44pin 400mil TSOP(II)
When setting /LB at a high level and other pins are in
an active state, upper-Byte are in a selectable mode
in which both reading and writing are enable, and
lower-Byte are in a non-selectable mode. And when
setting /UB at a high level and other pins are in an
active state, lower-Byte are in a selectable mode in
which both reading and writing are enable, and
upper-Byte are in a non-selectable mode.
When setting /LB and /UB at a high level or /S at high
level, the chip is in a non-selectable mode in which
both reading and writing are disabled. In this mode,
the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory
expansion by /LB, /UB and /S.
Signal-/S controls the power-down feature. When /S
goes high, power dissapation is reduced extremely.
The access time from /S is equivalent to the address
access time.
MITSUBISHI
ELECTRIC
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