MT9074 Datasheet, PDF (90/122 Pages) Mitel Networks Corporation – T1/E1/J1 Single Chip Transceiver

MT9074
Advance Information
Bit Name
Functional Description
7-2 - - - Unused
1-0 EC9-8 E bit Error Counter. The most
significant 2 bits of the E bit error
counter.
Table 120 - E-bit Error Counter
(Page 4, Address 14H) (E1)
Bit Name
Functional Description
7-2 - - - Unused
1-0 CC9 - 8 CRC-4 Error Counter These are the
most significant eight bits of the
CRC-64error counter.
Table 124 - CRC-4 Error Counter CEt
(Page 4, Address 18H) (E1)
Bit Name
Functional Description
7 - 0 EC7-0 E bit Error Counter. The least
significant 8 bits of the E-bit error
counter.
Table 121 - E-bit Error Counter
(Page 4, Address 15H) (E1)
Bit Name
Functional Description
7 - 0 CC7 - 0 CRC-4 Error Counter. These are
the least significant eight bits of the
CRC-4 error counter.
Table 125 - CRC-4 Error Counter CEt
(Page 4, Address 19H) (E1)
Bit Name
Functional Description
7 - 0 BPV15 - 8 Most Significant Bits of the
BPV Counter. The most
significant eight bits of a 16 bit
counter that is incremented once
for every bipolar violation error
received.
Table 122 - Most Significant Bits of the BPV
Counter
(Page 4, Address 16H) (E1)
Bit Name
Functional Description
7 - 0 BPV7 - 0 Least Significant Bits of the BPV
Counter. The least significant eight
bits of a 16 bit counter that is
incremented once for every bipolar
violation error received.
Table 123 - Least Significant Bits of the BPV
Counter
(Page 4, Address 17H) (E1)
Bit Name
Functional Description
7 TFSYNI Terminal
Frame
Synchronization Interrupt.
When unmasked this interrupt
bit goes high whenever a
change of state of terminal
frame synchronization condition
exists. Reading this register
clears this bit.
6 MFSYNI Multiframe Synchronization
Interrupt. When unmasked this
interrupt bit goes high whenever
a change of state of multiframe
synchronization
condition
exists. Reading this register
clears this bit.
5 CRCSYNI CRC-4
Synchronization
Interrupt. When unmasked this
interrupt bit goes high whenever
change of state of CRC-4
synchronization
condition
exists. Reading this register
clears this bit.
4
AISI
Alarm Indication Signal
Interrupt. When unmasked this
interrupt bit goes high whenever
a change of state of received all
ones condition exists. Reading
this register clears this bit.
Table 126 - Interrupt Word Zero
(Page 4, Address 1BH) (E1)
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