MT9074 Datasheet, PDF (37/122 Pages) Mitel Networks Corporation – T1/E1/J1 Single Chip Transceiver

Advance Information
MT9074
PRBS counter overflow (PRBSO) interrupt (page 1,
address 1DH) is associated with this counter.
CRC Multiframe Counter for PRBS (PSM7-0)
This eight bit counter counts receive CRC-4
multiframes. It can be directly loaded via the
microport. The counter will also be automatically
cleared in the event that the PRBS error counter is
written to by the microport. This counter is located on
page 04H, address 11H.
Error Insertion
In T1 mode MT9074 has six types of error conditions
can be inserted into the transmit DS1 data stream
through control bits, which are located on page 1,
address 19H - Error Insertion Word. These error
events include the bipolar violation errors (BPVE),
CRC-6 errors (CRCE), Ft errors (FTE), Fs errors
(FSE), payload (PERR) and a loss of signal condition
(LOSE). The LOSE function overrides the B8ZS
encoding function.
In E1 mode MT9074 has six types of error conditions
can be inserted into the transmit PCM 30 data
stream through control bits, which are located on
page 01H, address 19H. These error events include
the bipolar violation errors (BPVE), CRC-4 errors
(CRCE), FAS errors (FASE), NFAS errors (NFSE),
payload (PERR) and a loss of signal error (LOSE).
The LOSE function overrides the HDB3 encoding
function.
Per Time Slot Control Words
There are two per time slot control pages (addresses
AH and BH) (T1/E1) occupying a total of 24 unique
addresses in T1 mode or a total of 32 unique
addresses in E1 mode. Each address controls a
matching timeslot on the 24 DS1 channels (T1) or 32
PCM-30 channels (E1) and the equivalent channel
data on the receive (DSTo) data. For example
address 0 of the first per time slot control page
contains program control for transmit timeslot 0 and
DSTo channel 0.
Per Time Slot Control Word
Bit 7
T1 Mode
Bit 0
TXMSG PCI RTSL LTSL TTST RRST RPSIG CC
E1 Mode
TXMSG ADI RTSL LTSL TTST RRST RPSIG - - -
Clear Channel Capability
In T1 mode when bit zero (CC) in the per time slot
control word is set no bit robbing for the purpose of
signalling will occur in this channel. This bit is not
used in E1 mode.
Microport Signalling
When bit one (RPSIG) is set, the transmit signalling for
the addressed channel can only be programmed by
writing to the transmit signalling page (pages 5H and
6H) via the microport. If zero, the transmit signalling
information is constantly updated with the information
from the equivalent channel on CSTi.
Per Time Slot Looping
Any channel or combination of channels may be
looped from transmit (sourced from DSTi) to receive
(output on DSTo) STBUS channels. When bit four
(LTSL) in the Per Time Slot Control Word is set the
data from the equivalent transmit timeslot is looped
back onto the equivalent receive channel.
Any channel or combination of channels may be
looped from receive (sourced from the line data) to
transmit (output onto the line) channels. When bit
five (RTSL) in the Per Time Slot Control Word is set
the data from the equivalent receive timeslot is
looped back onto the equivalent transmit channel.
PRBS Testing
If the control bit ADSEQ is zero (from master control
page 1 - access control word), any channel or
combination of transmit channels may be
programmed to contain a generated pseudo random
bit sequence (2¹⁵ -1). The channels are selected by
setting bit three (TTST), in the per time slot control
word.
If the control bit ADSEQ is zero, any combination of
receive channels may be connected to the PRBS
decoder (2¹⁵-1). Each error in the incoming
sequence causes the PRBS error counter to
increment. The receive channels are selected by
setting bit 2 (RRST) in the per time slot control word.
If PRBS is performed during a metallic or external
looparound, per time slot control words with TTST
set should have RRST set as well.
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