MT90220 Datasheet, PDF (84/116 Pages) Mitel Networks Corporation – Octal IMA/UNI PHY Device

MT90220
Address (Hex):
Direct access
Reset Value (Hex):
219 - 220
1 Enable register per link Status reg
00
Bit #
7:0
Type
R/W
Description
Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in
the IRQ Link Status register is set.
Table 98 - IRQ Link Enable Registers
Address (Hex):
235
Direct access
Reset Value (Hex): XD
Bit #
7:4
3:0
Type
R
R/W
Description
Reserved.
Each bit set to ’1’ represent an overflow condition from the IMA Group associated with the
bit. There is one bit for each IMA Group. A bit is set when one or more of the 4 counters
or the RX UTOPIA FIFO associated with an IMA Group overflows.
Table 99 - IRQ IMA Group Overflow Status Register
Address (Hex):
204
Direct access
Reset Value (Hex): 00
Bit #
7:4
3:0
Type
R
R/W
Description
Unused. Should read 0’s.
Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in
the IRQ IMA Group Overflow Status register is set. There is one bit for each status bit.
Table 100 - IRQ IMA Group Overflow Enable Register
Address (Hex):
Direct access
Reset Value (Hex):
210 - 213
1 register per IMA Group. The RxClk and TxClk signals must be active for correct
register operation
00
Bit #
7:5
4
3
2
1
0
Type
R
R/W
R/W
R/W
R/W
R/W
Description
Unused. Should read 0’s.
This bit is set when the RX UTOPIA FIFO associated with an IMA Group overflows. This
bit is cleared by writing 0.
This bit is set when the counter for all cells associated with an IMA Group overflows.
(Input UTOPIA port). This bit is cleared by writing 0.
This bit is set when the counter for Idle Cells associated with an IMA Group overflows.
(Input UTOPIA port). This bit is cleared by writing 0.
This bit is set when the counter for Unassigned Cells associated with an IMA Group
overflows. (Input UTOPIA port). This bit is cleared by writing 0.
This bit is set when the counter for HEC Errored Cells associated with an IMA Group
overflows. (Input UTOPIA port). This bit is cleared by writing 0.
Table 101 - IRQ IMA Overflow Status Registers
76