MT90220 Datasheet, PDF (53/116 Pages) Mitel Networks Corporation – Octal IMA/UNI PHY Device

MT90220
7.2 TX Registers Description
Tables 23 to 37 describe the Transmit registers.
Address (Hex):
Direct access
Reset Value (Bin):
140
Used for initialization of the TX Cell RAM (Filler, Idle Cells etc.)
1X000000
Bit #
7
6
5
4:1
0
Type
R
R/W
R/W
R/W
R/W
Description
Goes to 0 during initialization and returns to 1 on completion of initialization.
Reserved, write 0 for normal operation.
Reserved. Write 0 for normal operation.
Reserved, write 0’s for normal operation.
Reserved. Write 0 to initialize the Cell RAM.
Table 23 - TX Cell RAM Control Register
Address (Hex):
150
Direct access
Reset Value (Hex): 00
Bit #
7:4
3:0
Type
W
W
Description
Write 0 for normal operation.
Write 1000 to load the TX Utopia FIFO level of IMA group 0
Write 1001 to load the TX Utopia FIFO level of IMA group 1.
Write 1010 to load the TX Utopia FIFO level of IMA group 2.
Write 1011 to load the TX Utopia FIFO level of IMA group 3.
7:5
R
Reserved, read 0’s.
4:0
R
Level of selected FIFO.
Table 24 - TX UTOPIA FIFO Level Register
Address (Hex):
14A
Direct access
Reset Value (Hex): 33
Bit #
7:4
3:0
Type
R/W
R/W
Description
TX FIFO Length Link 1.
TX FIFO Length Link 0.
Table 25 - TX FIFO Length Definition Register 1
Address (Hex):
14B
Direct access
Reset Value (Hex): 33
Bit #
7:4
3:0
Type
R/W
R/W
Description
TX FIFO Length Link 3.
TX FIFO Length Link 2.
Table 26 - TX FIFO Length Definition Register 2
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