PDSP16350_96 Datasheet, PDF (8/12 Pages) Mitel Networks Corporation – I/Q Splitter/NCO

PDSP16350
Modulated Frequency
the transmitter, and the other for the receiver. The phase
increment value is supplied by the counter block which simply
The output frequency can be modulated very simply, see
Fig 8. Since the phase increment value can be loaded as a
increments at a rate determined by dividing down the time
base clock. The synthesised frequency thus increases during
complete word every cycle, there is no need to provide internal
double buffering to prevent spurious frequencies being gener-
ated during the load operation. Binary Frequency Shift Keyed
(BFSK) modulation can easily be implemented by externally
the sweep period.
A number of the more significant phase increment bits are
used to supply the addresses to a PROM. The output of this
PROM is used to amplitude modulate the sine and cosine
multiplexing between two phase increment values represent- waveforms. In this manner it is possible to compensate, at the
ing the two frequencies to be used. The value to be used can
be instantaneously changed, thus maintaining phase coher-
source, for any poor frequency versus gain characteristics of
analog circuits further along in the system.
ence, whilst the bit to be transmitted changes from a mark to
a space. Frequency hopping could also be simply effected by
The digital outputs directly drive two D/A converters. Once
in the analog world, it is necessary to remove the alias
clocking a new random number into the DIN port once every frequencies with low pass filters. The phase linearity and pass
thousand cycles, for instance. The output will reflect any
change in the frequency after 31 system clock cycles.
If the phase increment value on the DIN port is changed on
band ripple characteristics of these filters are very important,
if the correct phase relationships are to be maintained be-
tween the two waveforms.
each clock cycle, then the output frequency will change
without introducing any dis-
continuities. Thus, a linear
frequency sweep can be
achieved by incrementing the
value on the DIN port by a
fixed amount each cycle. Al-
ternatively, a logarithmic
SWEEP
GENERATOR
Gain
Compensate
ROM
sweep could be implemented
by ‘walking’ a one across the
DIN port. Shifting the input
D17:0
D33:18
one place to the left every
hundred cycles, for example,
D/A
SIN
would double the frequency
every time.
PDSP
Chirp generation for FM -
CW Radar systems is a typi-
16 bit
Cordic
Sin / Cos
16350
cal example of the need for
Generator
D/A
COS
linear frequency sweeps. This
application requires the gen-
eration of quadrature chirp
waveforms and is illustrated
in simplified form by Fig. 7.
One waveform is needed for
Fig. 7 Quadrature Chirp Generator
CLK
MODE
RESET
JUMP
DATA IN
RESULT
12345
ABCD
30 31 32 33 34 35
ABCD
Device Reset Apply First Data
First Result Available
Fig. 8 Frequency Modulation Timing Diagram
8