MT90221 Datasheet, PDF (69/114 Pages) Mitel Networks Corporation – Quad IMA/UNI PHY Device

MT90221
7.7 RX Delay Registers Description
Tables 65 to 74 describe the RX Delay registers.
Address (Hex):
280
Synchronized access
Reset Value (Bin): 1X000000
Bit #
7
6
5
4
3
2
1:0
Type
R
R
R/W
R/W
R/W
R/W
R/W
Description
Upon a write to this register, the bit will go to 0 and will return to 1 when the transfer is
completed
Toggle Bit.
Write 0 to initiate a transfer from the MT90221 registers to the external RAM.
Write 1 to initiate a transfer from the external RAM to the MT90221 registers.
Reserved, write 0 for normal operation.
When Test Mode bit is 1; write 1 to enable the direct addressing mode to the External
SRAM.
When Test Mode bit is 1; write 0 for normal operation.Write 1 for disabling all access to
the external RAM except for the uP port (for RAM test purposes)
When bit 1 is 1, there is no access to the external RAM (no reset or read or write action to
the external RAM is done).
When bit 1 is 0 and bit 0 is 0, then the external RAM is initialized.
When bit 1 is 0 and bit 0 is 1, then a read or write access to the external RAM is
performed, as defined by bit 5.
Table 65 - RX External SRAM Control Register
Address (Hex):
Direct access
Reset Value (Hex):
281
Used to increment or decrement the recombiner delay for an IMA Group.
The value is in the Guardband/Delta Delay register
00
Bit #
7
6
5
4
3
2
1
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Write a 1 to decrement the recombiner delay of IMA Group #3. The bit will return to 0
when the delay is adjusted. Writing a 0 has no effect.
Write a 1 to increment the recombiner delay of IMA Group #3. The bit will return to 0 when
the delay is adjusted. Writing a 0 has no effect.
Write a 1 to decrement the recombiner delay of IMA Group #2. The bit will return to 0
when the delay is adjusted. Writing a 0 has no effect.
Write a 1 to increment the recombiner delay of IMA Group #2. The bit will return to 0 when
the delay is adjusted. Writing a 0 has no effect.
Write a 1 to decrement the recombiner delay of IMA Group #1. The bit will return to 0
when the delay is adjusted. Writing a 0 has no effect.
Write a 1 to increment the recombiner delay of IMA Group #1. The bit will return to 0 when
the delay is adjusted. Writing a 0 has no effect.
Write a 1 to decrement the recombiner delay of IMA Group #0. The bit will return to 0
when the delay is adjusted. Writing a 0 has no effect.
Write a 1 to increment the recombiner delay of IMA Group #0. The bit will return to 0 when
the delay is adjusted. Writing a 0 has no effect.
Table 66 - Increment/Decrement Delay Control Register
61