MT90221 Datasheet, PDF (15/114 Pages) Mitel Networks Corporation – Quad IMA/UNI PHY Device

MT90221
Pin Description (continued)
Pin #
Name I/O
Description
81, 88, 90, NC
97, 120,
122, 129,
131
No Connect. Can be left unconnected.
System Signals
74
Clk
I System Clock (25 MHz nominal). In the MT90221, this clock is used for all
internal operations of the device.
76
Test1 I Test1. This signal should be pulled up for normal operation.
54
Reset I System Reset. This is an active low input signal. It causes the device to enter the
initial state. The Clk signal must be active to reset the internal registers.
72
TCK
I JTAG Test Clock. It should be pulled down if not used
71
TMS
I JTAG Test Mode Select. TMS is sampled on the rising edge of TCK. TMS has an
internal pull- up resistor.
70
TDI
I JTAG Test Data Input.
68
TDO O JTAG Test Data Output. Note: TDO is tristated by TMS pin.
69
TRST I TAG Test Reset (active low). Should be asserted LOW on power-up and during
reset. Must be HIGH for JTAG boundary-scan operation. Note: This pin has an
internal pull-down.
77
Test2 I Test2. It should be pulled down for normal operation.
153
Test3 I Test3. It should be pulled down for normal operation.
152
Test4 I Test4. It should be pulled up for normal operation. NOT 5V TOLERANT
Notes:
1. Static memory stores the received cells. RAM is used for reordering the cells
2. These signals are used to transfer data between the MT90221 and the local processor
Pinout Summary
Type
TX UTOPIA
RX UTOPIA
Microprocessor Interface
External Memory Interface
TX PCM Interface
RX PCM Interface
PLL Interface
Miscellaneous
No Connect
Power
Ground
Total
208
Input
Output
I/O
16
1
7
10
14
1
8
22
8
4
8
12
4
2
10
1
63
41
24
N.C.
Power
Ground
24
25
31
24
25
31
7