SP5668 Datasheet, PDF (5/12 Pages) Mitel Networks Corporation – 2.7GHz 3-Wire Bus Controlled Synthesiser

SP5668
PHASE NOISE
The SP5668 has been designed to offer good phase noise
performance even when operated with a standard low profile
4MHz crystal and a high comparison frequency, e.g. 2MHz.
The typical phase noise performance measured in the
standard application is contained in Table 4. It has been
demonstrated that even higher levels of performance will be
achieved in a tuner application.
TEST MODES
The programmable divider output divided by two Fpd/2 and
the comparison frequency Fcomp, can be switched to ports P0
and P1 respectively.
The charge pump can be forced to either source or sink
current, and may be disabled to high impedance state.
The varactor DRIVE output can be disabled by the OS bit
within the data word, so switching the external transistor 'OFF'
and allowing an external voltage to be written to the varactor
line for tuner alignment purposes.
The test modes are described in Table 2.
CLOCK
ENABLE
DATA ^MSB
2 ²⁶ 2 ²⁵ 2 ²⁴ 2 ²³ 2 ²² 2 ²¹ 2 ²⁰ 2 ¹⁹ 2 ¹⁸ 2 ¹⁷ 2 ¹⁶
2 ⁰ LSB
P2 P1 P0 TO OS CO R2 R1 R0 PE
FREQUENCY DATA
2¹⁶ to 2⁰
PE
R2 , R1 , R0
P2, P1, P0
CO
OS
T0
t : Programmable divider ratio control bits
: ÷2 Prescaler (Enable = 1, Disable = 0)
t : Reference divider ratio control bits (see Table 1)
t : Port control bits
t : Charge Pump current select (see Table 3)
t : Drive output disable switch
t : Test mode enable (see Table 2)
R2
R1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
P1
P0
X
X
0
0
0
1
1
0
1
1
X = Don't care
Fig. 3 Data format and timing
R0
RATIO
Comparison Frequency with a 4MHz
external reference
0
2
2MHz
1
4
1MHz
0
8
500kHz
1
16
250kHz
0
32
125kHz
1
64
62.5kHz
0
128
31.25kHz
1
256
15.625kHz
Table 1 Reference division ratio
T0
FUNCTIONAL DESCRIPTION
0
Normal operation
1
Charge pump sink. LOCK output = Lo Z
1
Charge pump source. LOCK output = Hi Z
1
Charge pump disable. LOCK output = Lo Z
1
Port P1 = Fcomp: Port 0 = Fpd/2
Table 2 Test modes
5