SP5668 Datasheet, PDF (4/12 Pages) Mitel Networks Corporation – 2.7GHz 3-Wire Bus Controlled Synthesiser

SP5668
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V_EE at 0V
Charateristics
Pin
Min
Supply voltage, V_CC
RF input voltage
12
-0.3
13, 14
RF input offset
13, 14 -0.3
Port output voltage
7-9
-0.3
7-9
-0.3
Total port current
7-9
REFoutput DC offset
10
-0.3
Lock output DC offset
11
-0.3
Lock output current
11
Charge pump DC offset
1
-0.3
Drive DC offset
16
-0.3
Crystal oscillator DC offset
2, 3
-0.3
Data, Clock & inputs
4,5,6
-0.3
Storage temperature
-55
Junction temperature
MP16 Thermal resistance
Chip to ambient
Chip to case
Power consumption
at V_CC = 5.5V
ESD protection
ALL
2
Max
7
2.5
V_CC+0.3
14
6
50
V_CC+0.3
V_CC+0.3
10
V_CC+0.3
V_CC+0.3
V_CC+0.3
V_CC+0.3
+150
+150
Units
V
Vp-p
V
V
V
mA
V
V
mA
V
V
V
V
°C
°C
111
°C/W
41
°C/W
407
mV
kV
Conditions
Port in off state
Port in on state
All ports off, prescaler enabled
MIL-STD 883 TM3015
FUNCTIONAL DESCRIPTION
The SP5668 contains all the elements necessary, with the
exception of a frequency reference, loop filter and external
high voltage transistor, to control a varicap tuned local oscil-
lator, so forming a complete PLL frequency synthesised
source. The device allows for operation with a high compari-
son frequency and is fabricated in high speed logic, which
enables the generation of a loop with good phase noise
performance. The RF preamplifier contains a selectable di-
vide by two for operation above 2.0GHz. Up to 2GHz the RF
input interfaces directly with the programmable divider, so
eliminating degradation in phase noise due to the prescaler
action. The block diagram is shown in Fig.2.
The SP5668 is controlled by a standard 3–wire bus com-
prising data, clock and enable inputs. The programming word
contains 27 bits. P0 - P2 are used for port selection, 2¹⁷ - 2⁰ set
the programmable divider ratio R2 - R0 select the reference
division ratio (Table1). C0 sets the charge pump current
(Table 3) and the remaining two bits T0, OS access test modes
and disable the varactor drive (Table 2).The programming
format is shown in Fig. 3.
The clock input is disabled by an enable low signal, data is
therefore only clocked into the internal shift registers during an
enable high and is loaded into the controlling buffers by an
enable high to low transition. This load is also synchronised
with the programmable divider so giving smooth fine tuning.
The RF signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider signals.
The output of the preamplifier is fed to the ÷ 2/1 selectable
prescaler and then to the 17 bit fully programmable divider,
which is of MN+A architecture. The M counter is 13 bit and the
A counter 4. If bit PE is set to a 0 the prescaler is disabled;
the control function PE cannot be used dynamically. The
output of the programmable divider is fed to the phase
comparator where it is compared in both phase and frequency
domain with the comparison frequency. This frequency is
derived either from the on board crystal controlled oscillator or
from an external source. In both cases the reference
frequency is divided down to the comparison frequency by the
reference divider which is programmable into 1 of 8 ratios as
described in Table 1.
The output of the phase comparator feeds the charge
pump and loop amplifier section, which when used with an
external high voltage transistor and loop filter integrates the
current pulses into the varactor line voltage. The charge pump
current is selected by bit C0 as described in Table 3.
The phase comparator also drives the lock detect circuit
which generates a lock flag. 'In-lock' is indicated by a high
impedance state on the lock output.
The crystal frequency Fref is available at the REF output.
This may be used as the reference for a second synthesiser
as shown in Fig. 6. The REF output is disabled by connecting
the output, pin 3, to V_CC.
4