SP5659 Datasheet, PDF (5/12 Pages) Mitel Networks Corporation – 2·7GHz I2C Bus Low Phase Noise Synthesiser

The POR is reset to 0 when the read sequence is terminated
by a STOP command. When POR is set high (at low V_CC), the
programmed information is lost and the output ports are all set
to high impedance.
Bit 2 (FL) indicates whether the device is phase locked, a
logic ‘1’ is present if the device is locked, and a logic ‘0’ if the
device is unlocked.
Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of
the ADC. The ADC can be used to feed AFC information to the
microprocessor via the I²C bus.
Additional Programmable Features
Prescaler enable
The 42 prescaler is enabled by setting bit PE in byte 4 to
a logic ‘1’. A logic ‘0’ disables the prescaler, directly passing
the RF input to the 17-bit counter. Bit PE is a static select only.
SP5659
Charge pump current
The charge pump current can be programmed by bits C1 and
C0 in data byte 5, as defined in Fig. 3, Table 7.
Test mode
The test modes are invoked by setting bit RE to logic ‘0’ and
bit RTS to logic ‘1’ within the programming data and are selected
by bits TS2, TS1 and TS0 as shown in Fig. 3, Table 6. When TS2,
TS1 and TS0 are received, the device retains previously P2, P1
and P0 data.
Reference comparison frequency output
The reference frequency F_REF can be switched to the REF/
COMP output (pin 3) by setting byte 5 bit RE to logic ‘1’ and bit
RTS to logic ‘0’. The comparison frequency F_COMP can be
switched to the REF/COMP output by setting bit RE to logic ‘1’
and bit RTS to logic ‘1’. For RE set to logic ‘0’, the output is
disabled and set to a high state. RE and RTS default to logic ‘1’
during power-up, thus enabling F_COMP at the REF/COMP output.
MSB
LSB
Address
1 1 0 0 0 MA1 MA0 0
A
Programmable divider 0 2¹⁴ 2¹³ 2¹² 2¹¹ 2¹⁰
2⁹
2⁸
A
Programmable divider 2⁷ 2⁶ 2⁵ 2⁴ 2³ 2²
2¹
2⁰
A
Control data
1 2¹⁶ 2¹⁵ PE R3 R2
R1
R0
A
Control data
C1 C0 RE RTS P3 P2/TS2 P1/TS1 P0/TS0 A
Table 1 Write data format (MSB transmitted first)
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Address
Status byte
1 1 0 0 0 MA1 MA0 1 A Byte 1
POR FL X X X A2 A1 A0 A Byte 2
Table 3 Read data format
A2 A1 A0 Voltage on ADC input
1 00
0 11
0 10
0 01
0 00
0·6V_CC to V_CC
0·45V_CC to 0·6V_CC
0·3V_CC to 0·45V_CC
0·15V_CC to 0·3V_CC
0V to 0·15V_CC
Table 4 ADC levels
MA1 MA0 Address input voltage level
00
01
0V to 0·1V_CC
Open circuit
10
0·4V_CC to 0·6V_CC
11
0·9V_CC to V_CC
Table 5 Address selection
A
: Acknowledge bit
MA1, MA0
2¹⁶-2⁰
: Variable address bits (see Table 5)
: Programmable division ratio control bits
PE
: Prescaler enable
R3, R2, R1, R0 : Reference division ratio select (see Table 1)
C1, C0
: Charge pump current select (see Table 7)
RE
: Reference oscillator output enable
RTS
: REF/COMP select when RE = 1, Test mode enable when RE = 0 (see Table 6)
TS2, TS1, TS0 : Test mode control bits (valid when RE = 0 and RTS = 1,see Table 6)
P0
: Port P0 output state (always valid except when RE = 0 and RTS = 1 (see Table 6)
P3, P2, P1
: Ports P2, P1 and P0 output states
POR
: Power on reset indicator
FL
: Phase lock flag
A2, A1, A0
: ADC data (see Table 4)
X
: Don’t care
Fig. 3 Data formats
cont…
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