SP5659 Datasheet, PDF (4/12 Pages) Mitel Networks Corporation – 2·7GHz I2C Bus Low Phase Noise Synthesiser

SP5659
FUNCTIONAL DESCRIPTION
The SP5659 contains all the elements necessary – with
the exception of a frequency reference, loop filter and external
high voltage transistor – to control a varactor tuned local
oscillator, so forming a complete PLL frequency synthesised
source. The device allows for operation with a high comparison
frequency and is fabricated in high speed logic which enables
the generation of a loop with good phase noise performance.
The block diagram is shown in Fig. 2.
The RF input signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider signals.
The output of the preamplifier interfaces with a 17-bit fully
programmable divider via a 42 prescaler. For applications up
to 2·0GHz RF input, the prescaler can be disabled, so
eliminating the degradation in phase noise due to prescaler
action. The divider is of MN1A architecture, where N = 16 or
17, the M counter is 13 bits and the A counter is 4 bits.
The output of the programmable divider, F_PD, is fed to the
phase comparator where it is compared in phase and frequency
domains with the comparison frequency F_COMP. This frequency
is derived either from the on-chip crystal controlled oscillator
or from an external reference source. In either case, the
reference frequency F_REF is divided down to the comparison
frequency by the reference divider, which is programmable to
one of 15 ratios as detailed in Table 1.
The output of the phase detector feeds a charge pump and
loop amplifier section which, when used with an external high
voltage transistor and loop filter, integrates the current pulses
into the varactor line voltage. By invoking the device test
modes as described in Fig. 3, Table 6, the varactor drive
output can be disabled, so switching the external transistor
off. This allows an external voltage to be applied to the
varactor line for tuner alignment purposes. Similarly, the
charge can also be disabled to a high impedance state.
The programmable divider output F_PD/2 can be switched to
port P0 by programming the device into test mode as set out
in Table 6.
PROGRAMMING
The SP5659 is controlled by an I²C Bus. Data and Clock
are fed in on the SDA and SCL lines respectively, as defined
by the I²C Bus format. The synthesiser can either accept new
data (write mode) or send data (read mode). The LSB of the
address byte (R/W) sets the device into write mode if it is low
and read mode if it is high. Tables 1 and 2 in Fig. 3 illustrate
the format of the data. The device can be programmed to
respond to several addresses, which enables the use of more
than one synthesiser in an I²C Bus system. Table 4 in Fig. 3
shows how the address is selected by applying a voltage to
the address input.
When the device receives a valid address byte, it pulls the
SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are
programmed. When the device is programmed into the read
mode, the controller accepting the data must pull the SDA line
low during all status byte acknowledge periods to read an-
other status byte. If the controller fails to pull the SDA line low
during this period, the device generates an internal STOP
condition, which inhibits further reading.
WRITE Mode (Frequency Synthesis)
With reference to Table 2, bytes 2 and 3 contain frequency
information bits 2¹⁴ to 2⁰ inclusive. Auxiliary frequency bits 2¹⁶
and 2¹⁵ are in byte 4. For most frequencies, only bytes 2 and
3 will be required. The remainder of byte 4 and byte 5 control
the prescaler enable, reference divider ratio (see Fig. 3),
output ports and test modes (see Table 6).
After reception and acknowledgment of a valid address
(byte 1), the first bit of the following byte determines whether
the byte is interpreted as byte 2 (logic ‘0’) or byte 4 (logic ‘1’);
4
the next data byte is then interpreted as byte 3 or byte 5,
respectively. After two complete data bytes have been re-
ceived, additional data bytes can be entered, where byte
interpretation follows the same procedure without readdress-
ing the device. This procedure continues until a STOP condi-
tion is received. The STOP condition can be generated after
any data byte; if, however, it occurs during a byte transmis-
sion then the previous data is retained.
To facilitate smooth fine tuning, the frequency data bytes are
only accepted by the device after all 17 bits of the data have
been received or after the generation of a STOP condition.
Repeatedly sending bytes 2 and 3 only will not change the
frequency. A frequency change when one of the following
data sequences is sent to an addressed device:
Bytes 2, 3, 4, 5
Bytes 4, 5, 2, 3
or when a STOP condition follows valid data bytes thus:
Bytes 2, 3, 4, STOP
Bytes 4, 5, 2, STOP
Bytes 2, 3, STOP
Bytes 2, STOP
Bytes 4, STOP
It should be noted that the SP5569 must be addressed
initially with both frequency AND control byte data, since the
control byte contains reference divider information which
must be provided before a chosen frequency can be synthe-
sised. This implies that after initial turn on, bytes 2, 3 and 4
must be sent followed by a STOP condition as a minimum
requirement. Alternatively, bytes 2, 3, 4 and 5 must be sent if
port information is also required.
READ Mode
When the device is in read mode the status byte read from
the device on the SDA line takes the form shown in Fig. 3,
Table 3.
Bit 1 (POR) is the power-on reset indicator and is set to a
logic ‘1’ if the V_CC supply to the device has dropped below 3V
(at 25˚C), for example, when the device is initially turned on.
R3 R2 R1 R0 Ratio Comparison frequency
0 00 0
2
2MHz
0 00 1
4
1MHz
0 01 0
8
500kHz
0 0 1 1 16
250kHz
0 1 0 0 32
125kHz
0 1 0 1 64
62·5kHz
0 1 1 0 128
31·25kHz
0 1 1 1 256
15·625kHz
1 0 0 0 Invalid
1 00 1
5
800kHz
1 0 1 0 10
400kHz
1 0 1 1 20
200kHz
1 1 0 0 40
100kHz
1 1 0 1 80
50kHz
1 1 1 0 160
25kHz
1 1 1 1 320
12·5kHz
Table 1 Reference division ratios (4MHz external reference)