SP5769 Datasheet, PDF (4/11 Pages) Mitel Networks Corporation – 3GHz I2C Bus Synthesiser

SP5769
R3 R2 R1 R0
0000
0001
0010
0011
0100
0101
0110
0111
Division ratio
2
4
8
16
32
64
128
256
1000
24
1001
5
1010
10
1011
20
1100
40
1101
80
1110
160
1111
320
Table 1 Reference division ratios
Write mode
With reference to Table 2, bytes 2 and 3 contain frequency
information bits 2¹⁴-2⁰ inclusive. Bytes 4 and 5 control the
reference divider ratio (see Table 1), charge pump setting
(see Table 6), REF/COMP output (see Table 7), output
ports and test modes (see Table 5).
After reception and acknowledgement of a correct address
(byte 1), the first bit of the following byte determines whether
the byte is interpreted as a byte 2 or 4, a logic ‘0’ indicating
byte 2, and a logic ‘1’ indicating byte 4. Having interpreted
this byte as either byte 2 or 4, the following data byte will
be interpreted as byte 3 or 5 respectively. Having received
two complete data bytes, additional data bytes can be
entered, where byte interpretation follows the same
procedure, without re-addressing the device. This
procedure continues until a STOP condition is received.
The STOP condition can be generated after any data byte,
if however it occurs during a byte transmission, the previous
byte data is retained. To facilitate smooth fine tuning, the
frequency data bytes are only accepted by the device after
all 15 bits of frequency data have been received, or after
the generation of a STOP condition.
Read mode
When the device is in read mode, the status byte read
from the device takes the form shown in Table 3.
Bit 1 (POR) is the power-on reset indicator, and this is set
to a logic ‘1’ if the V_CC supply to the device has dropped
below 3V (at 25°C ), e.g. when the device is initially turned
on. The POR is reset to ‘0’ when the read sequence is
terminated by a STOP command. When POR is set high
this indicates the programmed information may be
corrupted and the device reset to power up condition.
Bit 2 (FL) indicates whether the device is phase locked, a
logic’1’is present if the device is locked, and a logic ‘0’ if it
is not.
Programable features
G RF programmable divider Function as described
above.
G Reference programmable divider Function as
described above.
G Charge pump current The charge pump current can
be programmed by bits C1 and C0 within data byte 5,
as defined in Table 6.
G Test mode The test modes are invoked by setting bit
T2 = 1, with selected test modes as defined by bits T1
and T0 as described in Table 5. Clock input on crystal
and RF input pins are required to invoke FL test modes.
G Reference/Comparison frequency output The
reference frequency f_REF or comparison frequency f_COMP
can be switched to the REF/COMP output, function as
defined in Table 7. RE and RS default to logic’1’during
device power up, thus enabling the comparison
frequency f_COMP at the REF/COMP output.
Address
Programmable divider
Programmable divider
Control data
Control data
MSB
LSB
1
1
0
0
0
MA1 MA0
0
0
2¹⁴
2¹³
2¹²
2¹¹
2¹⁰
2⁹
2⁸
2⁷
2⁶
2⁵
2⁴
2³
2²
2¹
2⁰
1
T2
T1
T0
R3
R2
R1
R0
C1
C0
RE
RS
P3
P2
P1
P0
Table 2 Write data format (MSB transmitted first)
A
MA1, MA0
2¹⁴-2⁰
R3-R0
C1, C0
RE
RS
T2-T0
P3-P0
Acknowledge bit
Variable address bits (see Table 4)
Programmable division ratio control bits
Reference division ratio select (see Table 1)
Charge pump current select (see Table 6)
Reference oscillator output enable
REF/COMP output select when RE=1 (see Table 7)
Test mode control bits (see Table 5)
P3, P2, P1 and P0 port output states
A Byte 1
A Byte 2
A Byte 3
A Byte 4
A Byte 5
4