SP5769 Datasheet, PDF (1/11 Pages) Mitel Networks Corporation – 3GHz I2C Bus Synthesiser

Features
G Complete 3·0 GHz Single Chip System
G Optimised for Low Phase Noise, with Comparison
Frequencies up to 4 MHz
G No RF Prescaler
G Selectable Reference Division Ratio
G Selectable Reference/Comparison Frequency Output
G Selectable Charge Pump Current with 10:1 Ratio
G Four Selectable I²C Addresses
G I²C Fast Mode Compliant with 3·3V and 5V Logic Levels
G Four Switching Ports
G Functional Replacement for SP5659 (except ADC)
G Pin Compatible with SP5655
G Power Consumption 110mW with V_CC = 5·5V, all Ports off
G ESD Protection 2kV min., MIL-STD-883B Method 3015
Cat.1 (Normal ESD handling procedures should be
observed)
Applications
G Digital Satellite and Cable Tuning Systems
G Communications Systems
The SP5769 is a single chip frequency synthesiser
designed for tuning systems up to 3GHz. The RF
preamplifier interfaces direct with the RF programmable
divider, which is of MN1A construction so giving a step
SP5769
3GHz I²C Bus Synthesiser
Preliminary information
DS4878 Issue 4.0 October 1999
Ordering Information
SP5769A/KG/MP1S (Tubes)
SP5769A/KG/MP1T (Tape and Reel)
SP5769A/KG/QP1S (Tubes)
SP5769A/KG/QP1T (Tape and Reel)
size equal to the loop comparison frequency and no
prescaler phase noise degradation over the full RF
operating range. The comparison frequency is obtained
either from an on-chip crystal controlled oscillator, or from
an external source. The oscillator frequency, f_REF, or phase
comparator frequency, f_COMP, can be switched to the REF/
COMP output providing a reference for a second frequency
synthesiser. The synthesiser is controlled via an 1²C bus
Absolute Maximum Ratings
All voltages are referred to V_EE = 0V
Supply voltage, V_CC
RF differential input voltage
0·3V to 17V
2·5Vp-p
All I/O port DC offsets
SDA and SCL DC offset
20·3 to V_CC 10·3V
20·3 to 6V
Storage temperature
255°C to 1125°C
Junction temperature
1150°C
MP16 thermal resistance
Chip to ambient, θ_JA
Chip to case, θ_JC
80°C/W
20°C/W
13
RF
INPUT ¹⁴
416/17
ADDRESS ¹⁰
SDA ⁴
SCL ⁵
I²C BUS
TRANSCEIVER
11-BIT
COUNT
4-BIT
COUNT
LOCK
fPD/2
REFERENCE
DIVIDER
ENABLE/
SELECT
PUMP
CP TEST
MODE SET
11 _REF/COMP
2 _{CRYSTAL CAP}
3 _CRYSTAL
1 _{CHARGE PUMP}
16 _DRIVE
15-BIT LATCH
2 BIT
4 BIT
2 BIT
3 BIT
4-BIT LATCH AND
PORT INTERFACE
67 89
P3 P2 P1 P0
Figure 1 SP5769 block diagram
fPD/2 SELECT