SP5669_97 Datasheet, PDF (4/12 Pages) Mitel Networks Corporation – 2.7GHz I2C Bus Controlled Synthesiser

SP5669
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V_EE at 0V.
Characteristics
Pin
Supply Voltage, V _CC
RF input voltage
RF input DC offset
Port voltage
Total port current
ADC input DC offset
REF/COMP output DC offset
Charge pump DC offset
Drive DC offset
Crystal oscillator DC offset
Address DC offset
SDA and SCL DC offset
Storage temperature
Junction temperature
MP16 thermal resistance
chip to ambient
chip to case
Power consumption at V CC =5.5V
ESD protection
12
13,14
13,14
7–10
7–10
7–10
11
3
1
16
2
4
5, 6
All
Value
Min
Max
0.3
7
2.5
–0.3
–0.3
V _CC +0.3
14
–0.3
6
50
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V +0.3
CC
V _CC +0.3
V _CC +0.3
V _CC +0.3
V _CC +0.3
V _CC +0.3
6V
–55
+150
+150
Units
V
V p–p
V
V
V
mA
V
V
V
V
V
V
V
°C
°C
111
°C/W
41
°C/W
468
mW
4
kV
Conditions
AC coupled as per application
Port in off state
Port in on state
All ports off, prescaler enabled
Mil Std 883 TM 3015
FUNCTIONAL DESCRIPTION
The SP5669 contains all the elements necessary, with the
exception of a frequency reference, loop filter and external high
voltage transistor, to control a varicap tuned local oscillator, so
forming a complete PLL frequency synthesised source. The
device allows for operation with a high comparison frequency
and is fabricated in high speed logic, which enables the
generation of a loop with good phase noise performance. The
block diagram is shown in Fig. 2.
The RF input signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider signals. The
output of the preamplifier interfaces with the 17–bit fully
programmable divider via a divide–by–two prescaler. For
applications up to 2GHz RF input, the prescaler may be disabled
so eliminating the degradation in phase noise due to prescaler
action. The divider is of MN+A architecture, where the dual
modulus prescaler is 16/17, the A counter is 4–bits, and the M
counter is 13–bits.
The output of the programmable divider is fed to the phase
comparator where it is compared in both phase and frequency
domain with the comparison frequency. This frequency is
derived either from the on–board crystal controlled oscillator or
from an external reference source. In both cases the reference
frequency is divided down to the comparison frequency by the
reference divider which is programmable into 1 of 15 ratios as
detailed in Fig. 3.
The output of the phase detector feeds a charge pump and
loop amplifier section, which when used with an external high
4
voltage transistor and loop filter, integrates the current
pulses into the varactor line voltage. By invoking the device
test modes as described in Fig. 5, the varactor drive output
can be disabled so switching the external transistor ’off’ and
allowing an external voltage to be written to the varactor line
for tuner alignment purposes. Similarly, the charge pump
may be also disabled to a high impedance state.
The programmable divider output Fpd/2 can be
switched to port P0 by programming the device into test
mode. The test modes are described in Fig. 5
PROGRAMMING
The SP5669 is controlled by an I ² C data bus. Data and
Clock are fed in on the SDA and SCL lines respectively as
defined by I²C bus format. The synthesiser can either
accept data (write mode) or send data (read mode). The
LSB of the address byte (R/W) sets the device into write
mode if it is low, and read mode if it is high. Tables 1 and 2
in Fig. 4 illustrate the format of the data. The device can be
programmed to respond to several addresses, which ena-
bles the use of more than one synthesiser in an I²C bus
system. Table 3 in Fig.4 shows how the address is selected
by applying a voltage to the ’address’ input. When the
device receives a valid address byte, it pulls the SDA line
low during the acknowledge period, and during following
acknowledge periods after further data bytes are received.
When the device is programmed into read mode, the
controller accepting the data must pull the SDA line low
during all status byte acknowledge periods to read another
status