SP5055 Datasheet, PDF (4/9 Pages) Mitel Networks Corporation – 2.6GHz Bidirectional I2C BUS Controlled Synthesiser

SP5055
Bits 3, 4 and 5 (I2,I1,I0) show the status of the I/O Ports P7,
P5 and P4 respectively. A logic 0 indicates a low level and a logic
1 a high level. If the ports are to be used as inputs they should
be programmed to a high impedance state (logic 1). These
inputs will then respond to data complying with TTL type voltage
levels. Bits 6, 7 and 8 (A2,A1,A0) combine to give the output of
the 5 level ADC.
The 5 level ADC can be used to feed AFC information to
the microprocessor from the IF section of the receiver, as
illustrated in the typical application circuit.
APPLICATION
A typical Application is shown in Fig. 4. All input/output
interface circuits are shown in Fig. 6.
MSB
LSB
Address
Programmable divider
Programmable divider
1 1 0 0 0 MA1 MA0 0 A
0 2¹⁴ 2¹³ 2¹² 2¹¹ 2¹⁰ 2⁹ 2⁸ A
2⁷ 2⁶ 2⁵ 2⁴ 2³ 2² 2¹ 2⁰ A
Charge pump and test bits 1 CP T1 T0 1 1 1 OS A
I/O port control bits
P7 P6 P5 P4 P3 X X P0 A
Table 1 Write data format (MSB transmitted first)
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Address
Status byte
1 1 0 0 0 MA1 MA0 1 A Byte 1
POR FL I2 I1 I0 A2 A1 A0 A Byte 2
Table 2 Read data format (MSB is transmitted first)
A
MA1, MA0
CP
T1
T0
OS
P7, P6, P5, P4,
P3, P0
POR
FL
I2, I1, I0
A2, A1, A0
X
: Acknowledge bit
: Variable address bits (see Table 4)
: Charge Pump current select
: Test mode selection
: Charge pump disable
: Varactor drive Output disable Switch
: Control output states
: Power On Reset indicator
: Phase lock detect flag
: Digital information from Ports P7, P5 and P4, respectively
: 5 Level ADC data from P6 (see Table 3)
: Don't care
A2 A1 A0 Voltage input to P6
1 0 0 0.6V_CC to 13.2V
0 1 1 0·45V_CC to 0·6V_CC
0 1 0 0·3V_CC to 0·45V_CC
0 0 1 0·15V_CC to 0·3V_CC
0 0 0 0 to 0.15V_CC
Table 3 ADC levels
MA1 MA0 Voltage input to P3
00
01
0V to 0·2V_CC
Always valid
1 0 0·3V_CC to 0·7V_CC
11
0·8V_CC -13.2V
Table 4 Address selection
Fig. 3 Data formats
4