SP5055 Datasheet, PDF (3/9 Pages) Mitel Networks Corporation – 2.6GHz Bidirectional I2C BUS Controlled Synthesiser

SP5055
Fig. 2 Block diagram
FUNCTIONAL DESCRIPTION
The SP5055 is programmed from an I²C BUS. Data and
Clock are fed in on the SDA and SCL lines respectively as
defined by the I²C BUS format. The synthesiser can either
accept new data (write mode) or send data (read mode). The
Tables in Fig. 3 illustrate the format of the data. The device
can be programmed to respond to several addresses, which
enables the use of more than one synthesiser in an I²C Bus
system. Table 4 shows how the address is selected by
applying a voltage to P3. The last bit of the address byte
(R/W) sets the device into read mode if it is high and write
mode if it is low. When the SP5055 receives a correct address
byte it pulls the SDA line low during the acknowledge period
and during following acknowledge periods after further data
bytes are programmed. When the SP5055 is programmed
into the read mode the controlling device accepting the data
must pull down the SDA line during the following acknowledge
period to read another status byte.
WRITE MODE (FREQUENCY SYNTHESIS)
When the device is in the write mode Bytes 2 + 3 select the
synthesised frequency while bytes 4 + 5 select the output port
states and charge pump information.
Once the correct address is received and acknowledged,
the first Bit of the next Byte determines whether that byte is
interpreted as byte 2 or 4, a logic 0 for frequency information
and a logic 1 for charge pump and output port information.
Additional data bytes can be entered without the need to
re-address the device until an I²C stop condition is recognised.
This allows a smooth frequency sweep for fine tuning or AFC
purposes.
If the transmission of data is stopped mid-byte (i.e., by
another device on the bus) then the previously programmed
byte is maintained.
Frequency data from bytes 2 and 3 is stored in a 15-bit shift
register and is used to control the division ratio of the 15-bit
programmable divider which is preceded by a divide-by-16
prescaler and amplifier to give excellent sensitivity at the local
oscillator input; see Fig 5. The input impedance is shown in
Fig 7.
The programmed frequency can be calculated by
multiplying the programmed division ratio by 16 times the
comparison frequency F_comp.
When frequency data is entered, the phase comparator,
via the charge pump and varactor drive amplifier, adjusts the
local oscillator control voltage until the output of the
programmable divider is frequency and phase locked to the
comparison frequency.
The reference frequency may be generated by an external
source capacitively coupled into pin 2 or provided by an on-
board 4MHz crystal controlled oscillator.
Note that the comparison frequency is 7·8125kHz when a
4MHz reference is used.
Bit 2 of byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for ±170µA and
a logic 0 for ±50µA, allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. Bit 4 of byte 4 (T0) disables the
charge pump if set to a logic 1. Bit 8 of byte 4 (OS) switches
the charge pump drive amplifier’s output off when it is set to
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the
phase comparator inputs are available on P6 and P7, a logic
1 connects F_comp to P6 and F_div to P7.
Byte 5 programs the output ports P0 to P7; on a logic 0 for
a high impedance output, logic 1 for low impedance (on).
READ MODE
When the device is in the read mode the status data read from
the device on the SDA line takes the form shown in Table 2.
Bit 1 (POR) is the power-on reset indicator and is set to a logic
1 if the power supply to the device has dropped below 3V and the
programmed information lost (e.g., when the device is initially
turned on). The POR is set to 0 when the read sequence is
terminated by a stop command. The outputs are all set to high
impedance when the device is initially powered up. Bit 2 (FL)
indicates whether the device is phase locked, a logic 1 is present
if the device is locked and a logic 0 if the device is unlocked.
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