SP5502 Datasheet, PDF (3/8 Pages) Mitel Networks Corporation – 1.3GHz I2C BUS 4-Address Synthesiser

The programmed frequency can be calculated by multiply-
ing the programmed division ratio by 8 times the comparison
frequency F_COMP.
When frequency data is entered, the phase comparator,
via the charge pump and varactor drive amplifier, adjusts the
local oscillator control voltage until the output of the program-
mable divider is frequency and phase locked to the comparison
frequency.
The reference frequency may be generated by an external
source capacitively coupled into pin 2 or provided by an on-
chip 4MHz crystal controlled oscillator.
Note that the comparison frequency is 7·8125kHz when a
4MHz reference is used.
Bit 2 of Byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for 6170µA and
a logic 0 for 650µA, allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. Bit 4 of Byte 4 (T0) disables the
SP5502
charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches
the charge pump drive amplifier’s output off when it is set to
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the
phase comparator inputs are available on P2 and P7, a logic
1 connects F_COMP to P2 and F_DIV to P7.
Byte 5 programs the output ports P0-P2, P4 and P7 on the
SP5502S (P1, P2 and P7 only on SP5502F), a logic 0 for a
high impedance output, logic 1 for low impedance (on).
READ MODE
When the device is in the read mode the status data read from
the device on the SDA line takes the form shown in Table 2. Bit
1 (POR) is the power supply to the device has dropped below a
nominal 3V and the programmed information lost (e.g., when the
device is initially turned on). The POR is set to 0 when the read
sequence is terminated by a stop command. The outputs are all
set to high impedance when the device is initially powered up. Bit
2 (FL) indicates whether the device is phase locked, a logic 1 is
present if the device is locked and a logic 0 if the device is
unlocked.
MSB
LSB
Address
Programmable divider
Programmable divider
1 1 0 0 0 MA1 MA0 0 A
0 2¹⁴ 2¹³ 2¹² 2¹¹ 2¹⁰ 2⁹ 2⁸ A
2⁷ 2⁶ 2⁵ 2⁴ 2³ 2² 2¹ 2⁰ A
Charge pump and test bits 1 CP T1 T0 1 1 1 OS A
I/O port control bits
P7 X X P4* X P2 P1 P0* A
Table 1 Write data format (MSB transmitted first)
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Address
Status byte
1 1 0 0 0 MA1 MA0 1
POR FL N N N N N N
Table 2 Read data format
A Byte 1
A Byte 2
MA1 MA0 Voltage input to P3
00
01
0V to 0·1V_CC
Open circuit
1 0 0·4V_CC to 0·6V_CC†
11
0·9V_CC to V_CC
Table 3 Address selection
A
:
MA1, MA0
:
CP
:
T1
:
T0
:
OS
:
P7, P4*, P2, P1, P0*
POR
:
FL
:
X
:
N
:
Acknowledge bit
Variable address bits (see Table 3)
Charge Pump current select
Test mode selection
Charge pump disable
Varactor drive Output disable Switch
: Control output port states
Power On Reset indicator
Phase lock detect flag
Don’t care
Not valid
NOTES
† Programmed by connecting a 15kΩ resistor between Address Select Port P3 and V_CC.
* ^{Don’t care condition on SP5502F.}
Fig. 3 Data formats
3