SP5502 Datasheet, PDF (2/8 Pages) Mitel Networks Corporation – 1.3GHz I2C BUS 4-Address Synthesiser

SP5502
ELECTRICAL CHARACTERISTICS
T_AMB = 210°C to 180°C, V_CC = 14·5V to 15·5V. All pin references are to the SP5502S (MP16 package).
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated.
Characteristic
Value
Pin
Units
Min. Typ. Max.
Conditions
Supply current
Prescaler input voltage
Prescaler input voltage
Prescaler input impedance
Prescaler input capacitance
12
48
13,14 12·5
30
13,14
50
2
60 mA V_CC = 5V
300 mVrms 80MHz to 1GHz
300 mVrms 1·3GHz, see Fig. 5
Ω
pF
SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
SDA
Output voltage
4,5
3
4,5
0
4,5
4,5
4,5
4
V_CC
V
1·5 V
10 µA Input voltage = V_CC
210 µA Input voltage = 0V
10 µA When V_CC = 0V
0·4 V Sink current = 3mA
Charge pump current low
Charge pump current high
Charge pump output leakage current
Charge pump drive output current
Charge pump amplifier gain
Recommended crystal series resistance
Crystal oscillator drive level
Crystal oscillator negative resistance
1
650
µA Byte 4, bit 2 = 0, pin 1 = 2V
1
6170
µA Byte 4, bit 2 = 1, pin 1 = 2V
1
65 nA Byte 4, bit 4 = 1, pin 1 = 2V
16
500
V pin 16 = 0·7V
6400
10
200
Ω Parallel resonant crystal (note 2)
40
2
750
mV p-p
Ω
Output Ports
Sink current
Leakage current
Input Port
P3 input current high
P3 input current low
6,7,9-11 20
6,7,9-11
8
8
mA V_OUT = 0·7V (see note 1)
10 µA V_OUT = 13·2V
1
mA V pin 8 = V_CC
20·5 mA V pin 8 = 0V
NOTES
1. Source impedance between all output ports and ground is approximately 5Ω. This should be taken into account when calculating output port
saturation voltages.
2. The maximum resistance quoted refers to all conditions, including start-up.
FUNCTIONAL DESCRIPTION (Except where
otherwise indicated, ‘SP5502’ refers to both
variants)
The SP5502 is programmed from an I²C BUS. Data and
Clock are fed in on the SDA and SCL lines respectively as
defined by the I²C Bus format. The synthesiser can either
accept new data (write mode) or send data (read mode). The
Tables in Fig. 3 illustrate the format of the data. The device
can be programmed to respond to several addresses, which
enables the use of more than one synthesiser in an I²C Bus
system. Table 3 shows how the address is selected by
applying a voltage to P3. The address input is shown in Fig.
6. The LSB of the address Byte (R/W) sets the device into read
mode if it is high and write mode if it is low. When the SP5502
receives a correct address Byte it pulls the SDA line low
during the acknowledge period and during following acknowl-
edge periods after further data Bytes are programmed. When
the SP5502 is programmed into the read mode the controlling
device accepting the data must pull down the SDA line during
the following acknowledge period to read another status Byte.
2
WRITE MODE (FREQUENCY SYNTHESIS)
When the device is in the write mode Bytes 213 select the
synthesised frequency while Bytes 415 select the output port
states and charge pump information.
Once the correct address is received and acknowledged,
the first Bit of the next Byte determines whether that Byte is
interpreted as Byte 2 or 4, a logic 0 for frequency information
and a logic 1 for charge pump and output port information.
Additional data Bytes can be entered without the need to re-
address the device until an I²C stop condition is recognised.
This allows a smooth frequency sweep for fine tuning or AFC
purposes.
If the transmission of data is stopped mid-byte (i.e., by
another device on the bus) then the previously programmed
byte is maintained.
Frequency data from Bytes 2 and 3 is stored in a 15-bit shift
register and is used to control the division ratio of the 15-bit
programmable divider which is preceded by a divide-by-8
prescaler and amplifier to give excellent sensitivity at the local
oscillator input; see Fig 5. The input impedance is shown in Fig
7.