PDSP1601_96 Datasheet, PDF (3/18 Pages) Mitel Networks Corporation – ALU and Barrel Shifter

PDSP1601/PDSP1601A
PIN DESCRIPTIONS
Symbol
Pin No.
(LC84
Package)
Description
MSB
2
ALU B-input multiplexer select control.¹ This input is latched internally on the rising edge
of CLK.
MSS
3
Shifter Input multiplexer select control.¹ This input is latched internally on the rising edge
of CLK.
B15 - B0
4 - 19
B Port data input. Data presented to this port is latched into the input register on the rising
edge of CLK. B15 is the MSB.
CEB
CLK
20
Clock enable, B Port input register. When low the clock to this register is enabled.
21
Common clock to all internal registered elements. All registers are loaded, and outputs
change on the rising edge of CLK.
MSA0 - MSA1 23 - 24
ALU A-input multiplexer select control.¹ These inputs are latched internally on the rising
edge of CLK.
A15 - A0
25 - 40
A Port data input. Data presented to this port is latched into the input register on the rising
edge of CLK. A15 is the MSB.
CEA
MSC
41
Clock enable, A Port input register. When low the clock to this register is enabled.
42
C-Port multiplexer select control.¹ This input is latched internally on the rising edge
of CLK.
IS0 - IS3
43 - 46
Instruction inputs to Barrel Shifter, IS3 = MSB.¹ These inputs are latched internally on the
rising edge of CLK.
SV0 - SV3 47 - 50
Shift Value I/O Port. This port is used as an input when shift values are supplied from
external sources, and as an output when Normalise operations are invoked. The I/O functions
are determined by the IS0 - IS3 instruction inputs, and by the SVOE control.
The shift value is latched internally on the rising edge of CLK.
SVOE
51
SV Output enable. When high the SV port can only operate as an input. When low the SV
port can act as an input or as an output, according to the IS0 - IS3 instruction. This pin should
be tied hihg or low, depending upon the application.
RS0, RS1
RS2
52 - 53
55
Instruction inputs to Barrel Shifter registers.¹ These inputs are latched internally on the
rising edge of CLK.
C0 - C15
56 - 63
65 - 72
C Port data output. Data output on this port is selected by the C output multiplexer.
C15 is the MSB.
OE
73
Output enable. The C Port outputs are in high impedance condition when this control is high.
BFP
74
Block Floating Point Flag from ALU, active high.
CO
76
Carry out from MSB of ALU.
RA0 - RA2 77 - 79
Instruction inputs to ALU registers.¹ These inputs are latched internally on the rising
edge of CLK.
CI
80
Carry in to LSB of ALU.
IA0 - IA3
IA4
81 - 84
1
Instruction inputs to ALU.¹ IA4 = MSB. These inputs are latched internally on the rising
edge of CLK.
Vcc
54 & 75 +5V supply: Both Vcc pins must be connected.
GND
22 & 64 0V supply: Both GND pins must be connected.
NOTES
1. All instructions are executed in the cycle commencing with the rising edge of the CLK which latches the inputs.
3