MT8920B-1 Datasheet, PDF (3/29 Pages) Mitel Networks Corporation – ISO-CMOS ST-BUS™ FAMILY ST-BUS Parallel Access Circuit

CMOS MT8920B
Pin Description (continued)
Pin # Name
Description^‡
13
A5 Address Bit A5 (Mode 1). This input is used to extend the address range of the STPA. A5
selects internal registers when high and Tx/Rx RAM’s when low.
A5 Address Bit A5 (Mode 2). This input is used to extend the address range of the STPA. A5
selects Tx0/Rx0 RAM’s when low and Tx1/Rx0 RAM’s when high.
STCH Start of Channel (Mode 3). This signal is a low going pulse which indicates the start of an
ST-BUS channel. The pulse is four bits wide and begins at the start of each valid channel.
14
15-22
V_SS Ground.
D0-D7 Bidirectional Data Bus. This bus is used to transfer data to or from the STPA during a write
or read operation.
23 STo0 ST-BUS Output 0. This output supplies the output ST-BUS 2048 kbit/s serial data stream from
Tx0 two-port RAM.
24 STo1 ST-BUS Output 1. In modes 1 and 2 this output supplies the output ST-BUS 2048 kbit/s serial
data stream from Tx1 two-port RAM. In mode 3, information arriving at STi0 is output here with
one frame delay.
25 IRQ Interrupt Request (Mode 1). This open drain output, when low, indicates when an interrupt
condition has been raised within the STPA.
24/32 24 Channel/32 Channel Select (Mode 2,3). This input is used to select the channel
configuration in modes 2 and 3. A low applied to this pin will select a 24 (T1) channel mode
while a high will select a 32 (CEPT) channel mode.
26 DTACK Data Transfer Acknowledge (Mode 1). This open drain output is supplied by the STPA to
acknowledge the completion of data transfers back to the µP. On a read of the STPA, DTACK
low indicates that the STPA has put valid data on the data bus. On a write, DTACK low
indicates that the STPA has completed latching the µP’s data from the data bus.
BUSY BUSY (Mode 2). This open drain output signals that the controller and the ST-BUS are
accessing the same location in the dual-port RAM’s. It is intended to delay the controller
access until after the ST-BUS completes its access.
DCS Delayed Chip Select (Mode 3). This low going pulse, which is four bit cells long, is active
during the last half of a valid channel. This signal is used to daisy-chain together two STPA’s in
mode 3 that are accessing devices on the same parallel data bus.
27 MMS Master Mode Select (Reset). This Schmitt trigger input selects between either mode 1 (MMS
= 1), or modes 2and 3 (MMS = 0). If MMS is pulsed low in Mode 1 operation the control and
interrupt registers will be reset. (Refer to Table 1.) During power-up, the time constant of the
reset circuit (see Fig. 8) must be a minimum of five times the rise time of the power supply.
28 V_DD Power Supply Input. (+5V).
‡ Pin Descriptions pertain to all modes unless otherwise stated.
Mode MMS MS1
1
1 N/A
2
0
1
3
0
0
Mode of
Operation
µP
Peripheral
Mode
Fast RAM
Mode
Bus
Controller
Mode
Function
The STPA provides parallel-to-serial and serial-to-parallel conversions through a
68000-type interface. Two Tx RAMs and one Rx RAM are available along with full
interrupt capability. 32 channel or 24 channel support is available. Control Register 1, bit
D₅ (RAMCON) = 0 for 32 channel operation and D₅ (RAMCON)= 1 for 24 channel
operation.
The STPA provides a fast access interface to Tx0, Tx1 and Rx0 RAMs. This mode is
intended for full parallel support of 24 channel T1/ESF trunks and 32 channel CEPT
trunks. Input 24/32 (pin 25) = 0 for 24 channel operation, input 24/32 (pin 25) = 1 for 32
channel operation.
The STPA will synchronously drive the parallel bus using the address generator and
provide all data transfer signals. This mode is intended to support 24 or 32 channel
devices in the absence of a parallel bus controller. Input 24/32 (pin 25) = 0 for 24 channel
operation, input 24/32 (pin 25) = 1 for 32 channel operation.
Table 1. STPA Modes of Operation
3-5