MT8920B-1 Datasheet, PDF (20/29 Pages) Mitel Networks Corporation – ISO-CMOS ST-BUS™ FAMILY ST-BUS Parallel Access Circuit

MT8920B CMOS
AC Electrical Characteristics^† - Mode 3 Timing (see Fig.17, 18 and 19)
((V_CC=5.0V ±5%,TA=-40 to 85°C)
Characteristics
Sym Min Typ^‡ Max Units
Test Conditions
1 CS to OE, WE, Address Enabled
2 C4i Low to Address Change
3 CS to OE, WE, Address Disabled
4 C4i Low to Output Enable Low
5 C4i Low to Output Enable High
6 OE, WE, Pulse Width
7 C4i Low to Write Enable Low
8 C4i Low to Write Enable High
9 Read Data Valid from OE
t_ZR
t_ACS
t_RZ
t_OED
t_OEH
t_ENPW
t_WED
t_WEH
t_RST
50
ns ^{Load A, C}L ^{= 130pF, R}L ^{= 740Ω}
110
ns ^{Load A, C}L ^{= 130pF, R}L ^{= 740Ω}
50
ns ^{Load A, C}L ^{= 130pF, R}L ^{= 740Ω}
75
ns ^{Load A, C}L ^{= 130pF, R}L ^{= 740Ω}
75
ns ^{Load A, C}L ^{= 130pF, R}L ^{= 740Ω}
2*t_CLK
ns ^{Load A, C}L ^{= 130pF, R}L ^{= 740Ω}
75
ns ^{Load A, C}L ^{= 130pF, R}L ^{= 740Ω}
75
ns ^{Load A, C}L ^{= 130pF, R}L ^{= 740Ω}
(2*t_CLK) ns
-60
10 Read Data Hold Time
t_RHT
0
ns
11 Write Data Setup Time
t_WST 70 100
ns ^{Load A, C}L ^{= 130pF, R}L ^{= 740Ω}
12 Write Data Hold Time
t_WHT 70 100
ns ^{Load A, C}L ^{= 130pF, R}L ^{= 740Ω}
13 C4i Transition to STCH, DCS Trans. t_STC
120
ns ^{Load A, C}L ^{= 70pF, R}L ^{= 1.22KΩ}
14 STCH Pulse Width
t_SCPW
1830
ns ^{Load A, C}L ^{= 70pF, R}L ^{= 1.22KΩ}
15 DCS Pulse Width
t_CSPW
1830
ns ^{Load A, C}L ^{= 70pF, R}L ^{= 1.22KΩ}
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C, V_DD=5V,t_CLK=244ns, t_CH=t_CL=122ns and are for design aid only: not guaranteed and not subject to production
testing.
BIT 7 (BIT 3)
CHANNEL N
BIT 6 (BIT 2)
BIT 5 (BIT 1)
BIT 4 (BIT 0)
C4i
A4 - A0
t_ACS
OE
WE
D7 - D0
t_ZR
CS
N+1
t_OED
t_ENPW
t_OEH
N-1
t_WED
t_WEH
t_RST
DATA IN
t_RHT
t_WST
t_ENPW
t_WHT
DATA OUT
t_RZ
Figure 17 - Mode 3 Timing Diagram
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