MT9161B Datasheet, PDF (24/30 Pages) Mitel Networks Corporation – ISO2-CMOS 5 Volt Multi-Featured Codec (MFC)

Advance Information
MT9160B/61B
t_R
CLOCKin _70%
(BCL)
30%
70%
Din
30%
Dout
70%
30%
t_DOZL
t_DOZH
STB
70%
30%
t_BCLH
t_BCL
t_F
t_BCLL
t_DIS
t_DIH
t_SSS
t_DD
t_ENW
t_SSH
t_DOLZ
t_DOHZ
70%
STBd
30%
t_DSTBR
NOTE: Levels refer to % V_DD (CMOS I/O)
Figure 12 - SSI Synchronous Timing Diagram
t_DSTBF
t_ENWD
AC Electrical Characteristics^† - SSI BUS Asynchronous Timing (note 1) (see figure 13)
Characteristics
Sym
Min
Typ^‡
Max Units Test Conditions
1 Bit Cell Period
T_DATA
7812
3906
ns BCL=128 kHz
ns BCL=256 kHz
2 Frame Jitter
3 Bit 1 Dout Delay from STB
going high
4 Bit 2 Dout Delay from STB
going high
5 Bit n Dout Delay from STB
going high
T_j
t_dda1
t_dda2
t_ddan
600+
T_DATA-T_j
600 +
(n-1) x
T_DATA-T_j
600
T_j+600
600+
T_DATA
600 +
(n-1) x
T_DATA
600 +
T_DATA+T_j
600 +
(n-1) x
T_DATA+T_j
ns
ns C_L=150 pF, R_L=1K
ns C_L=150 pF, R_L=1K
ns C_L=150 pF, R_L=1K
n=3 to 8
6 Bit 1 Data Boundary
T_DATA1 T_DATA-T_j
T_DATA+T_j
ns
7 Din Bit n Data Setup time from t_SU
T_DATA\2
STB rising
+500ns-T_j
+(n-1) x
T_DATA
ns n=1-8
8 Din Data Hold time from STB
t_ho
T_DATA\2
ns
rising
+500ns+T_j
+(n-1) x
T_DATA
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.
102