MT8889C Datasheet, PDF (2/18 Pages) Mitel Networks Corporation – Integrated DTMFTransceiver with Adaptive Micro Interface

MT8889C/MT8889C-1
IN+ 1
IN- ²
GS 3
VRef 4
VSS ⁵
OSC1 6
OSC2 7
TONE 8
R/W/WR 9
CS 10
20 _VDD
19 St/GT
18 ESt
17 D3
16 D2
15 D1
14 D0
13 IRQ/CP
12 _DS/RD
11 RS0
20 PIN CERDIP/PLASTIC DIP/SOIC
IN+ 1
24
IN- 2
23
GS 3
22
VRef 4
21
VSS ⁵
20
OSC1 6
19
OSC2 7
18
NC 8
17
NC 9
16
TONE ₁₀
15
R/W/WR 11
14
CS 12
13
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
Pin #
20 24 ^Name
Description
11
IN+ Non-inverting op-amp input.
2 2 IN- Inverting op-amp input.
33
GS Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4 4 V_Ref Reference Voltage output (V_DD/2).
5 5 V_SS Ground (0V).
6 6 OSC1 Oscillator input. This pin can also be driven directly by an external clock.
7 7 OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
8 10 TONE Output from internal DTMF transmitter.
9 11
10 12
R/W
(WR)
CS
(Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible.
Chip Select input. This signal must be qualified externally by either address strobe (AS),
valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
11 13 RS0 Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
12 14 DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only
required when the device is being accessed. TTL compatible.
13 15 IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
14- 18- D0-D3 Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
17 21
(Intel). TTL compatible.
18 22
ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
19 23
St/GT
Steering Input/Guard Time output (bidirectional). A voltage greater than V_TSt detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than V_TSt frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
20 24
8,9
16,
17
V_DD Positive power supply (5V typ.).
NC No Connection.
4-108