MT9173 Datasheet, PDF (15/22 Pages) Mitel Networks Corporation – Digital Subscriber Interface Circuit with RxSB

Preliminary Information
MT9173/74
Applications
Typical connection diagrams are shown in Figures 13
and 14 for the DN mode as a MASTER and SLAVE,
respectively. L_OUT is connected to the coupling
transformer through a resistor R2 and capacitors C2
and C2’ to match the line characteristic impedance.
Suggested values of R2, C2 and C2’ for 80 and 160
kbit/s operation are provided in Figures 13 and 14.
Overvoltage protection is provided by R1, D1 and
D2. C1 is present to properly bias the received line
signal for the L_IN input. A 2:1 coupling transformer is
used to couple to the line with a secondary center
tap for optional phantom power feed. Varistors have
been shown for surge protection against such things
as lightning strikes.
If the scramblers power up with all zeros in them,
they are not capable of randomizing all-zeros data
sequence. This increases the correlation between
the transmit and receive data which may cause loss
of convergence in the echo canceller and high bit
error rates.
In DN mode the insertion of the SYNC pattern will
provide enough pseudo-random activity to maintain
convergence. In MOD mode the SYNC pattern is not
inserted. For this reason, at least on ”1” must be fed
into the DNIC on power up to ensure that the
scramblers will randomize any subsequent all-zeros
sequence.
DV Port ST-BUS _{
CD Port ST-BUS {
Master Clocks {
Mode Select
Lines
+5V
0.33 µF
0.33 µF
To Time
Measurement
Circuitry
MT9173/74
DSTi
DSTo
CDSTi
CDSTo
F0
C4
MS0
MS1
MS2
V_Ref
V_Bias
L_OUT
L_IN
OSC1
OSC2
F0o
RxSB
C2’ = 1.5 nF
C2 = 22 nF
+5V
D1 = D2 = MUR405
For 80 kbit/s: C2’ = 3.3 nF
R2 = 390Ω
R1 = 47Ω
2:1
D2
D.C. coupled,
Frequency locked
10.24 MHz clock.
NC ^{Refer to AC Electrical}
Characteristics
Clock Timing
DN Mode.
C1 = 0.33 µF
Line Feed
Voltage
1.0 µF
68 Volts
(Typ)
2.5 Joules
0.02 Watt
To Next DNIC
Note: Low leakage diodes (1 & 2) are required so
that the DC voltage at L_IN ≈ V_Bias
Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s
DV Port ST-BUS _{
CD Port ST-BUS {
Master Clocks {
Mode Select
Lines
+5V
0.33 µF
0.33 µF
To hardware
SYNC
Indicator
(optional)
MT9173/74
DSTi
DSTo
CDSTi
CDSTo
L_OUT
F0
C4
L_IN
MS0
MS1
MS2
OSC1
V_Ref
V_Bias
RxSB
OSC2
C2’ = 1.5 nF
C2 = 22 nF
+5V
D1 = D2 = MUR405
For 80 kbit/s: C2’ = 3.3 nF
R2 = 390Ω
R1 = 47Ω
2:1
D2
10.24 MHz XTAL
1.0 µF _Supply
68 Volts
(Typ)
2.5 Joules
0.02 Watt
C3 = 33pF = C4
C1 = 0.33 µF
Note: Low leakage diodes (1 & 2) are required so
that the DC voltage at L_IN ≈ V_Bias
Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s
9-151